STM32L1 Training | Ac6 Formation

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STR17STM32L1
This course describe the STM32L1 architecture and practical examples

Objectives

  • Understand Cortex-M3 core and STM32L1 SoC.
  • Configure RCC (MSI/HSI/HSE/LSI/LSE) and PLL.
  • Use GPIO/EXTI, timers, DMA, ADC, serial I/O.
  • Apply ultra-low-power modes and measure impact.
  • Manage Flash, true Data EEPROM, Option Bytes, watchdogs.
  • (Variant) Bring up USB FS, LCD, TSC.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Practical activities (40-50% of duration)
    • Code examples, exercises and solutions.
    • Remote: one online Linux PC per trainee, with emulated or physical board as needed.
    • Face-to-face / on-site: one PC (one per two beyond six trainees), target board and install manual as needed.
  • Downloadable preconfigured VM to redo the labs afterwards.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the training.
  • Progress is assessed by the trainer through the practical exercises, and by quizzes for sections without exercises.
  • Each trainee receives a completion certificate.
  • If a prerequisite gap appears, alternative or additional training is offered.

Course Outline

  • Core overview
  • MSP/PSP stacks.
  • Exceptions, NVIC priority.
  • SysTick, SVC, PendSV.
  • Faults: HardFault path.
  • WFI/WFE basics.
Exercise:  Exception Management
  • Lines: L1x1/L1x2/L1x3.
  • Flash/SRAM/PPB layout.
  • Peripheral address map.
  • UID and Flash size regs.
  • Option Bytes snapshot.
Exercise:  Map & IDs
  • MSI ranges/accuracy.
  • HSI/HSE selection.
  • PLL M/N/R (device).
  • SYSCLK mux, AHB/APB.
  • CCIPR kernel clocks.
  • MCO output; CSS.
Exercise:  Clock profiles
  • Sleep/Low-power run.
  • Low-power sleep/Stop.
  • Standby + VBAT domain.
  • Voltage scaling ranges.
  • PVD/BOR.
Exercise:  Mode sweep
  • PP/OD, pulls, speeds.
  • AF mapping rules.
  • EXTI lines, priorities.
  • Debounce strategies.
  • Safe I/O at reset.
Exercise:  GPIO + EXTI
  • PWM edge/center.
  • Input capture.
  • One-pulse mode.
  • Encoder interface.
  • Master/slave triggers.
  • (Variant) LPTIM tickless.
Exercise:  PWM + capture
  • Channels/requests map.
  • Normal vs circular.
  • HT/TC/TE flags.
  • Throughput vs latency.
Exercise:  UART RX ring (DMA)
  • 12-bit ADC basics.
  • Sampling time, ranks.
  • Timer-triggered ADC.
  • DMA continuous/circular.
  • Analog watchdog.
  • Internal VREF/TEMP.
Exercise:  ADC + DMA stream
  • LSE vs LSI trade-offs.
  • Calendar, alarm, wakeup.
  • Backup registers.
  • Tickless via RTC/LPTIM.
  • Drift, calibration.
Exercise:  Tickless blink
  • USART Overview.
  • Blocking/IRQ/DMA.
  • Stop-mode wake (LPUART).
  • Error recovery (ORE/FE).
Exercise:  Robust UART
Exercise:  LPUART wake from Stop
  • CPOL/CPHA modes.
  • Data sizes; NSS rules.
  • Full-duplex DMA.
  • Simplex options.
  • Timing check (LA).
Exercise:  SPI loopback DMA
  • Sm/Fm/Fm+ speeds.
  • 7/10-bit addressing.
  • Analog/digital filters.
  • Timeouts; bus-clear.
  • Clock stretching.
  • VBUS sense options.
  • EP/FIFO basics.
  • CDC/DFU quick paths.
  • Clocking constraints.
  • Suspend/resume flow.
Exercise:  CDC echo or DFU
  • COM/SEG mapping.
  • Bias/duty settings.
  • Frame frequency.
  • Contrast options.
  • Simple icon drive.
Exercise:  LCD icon demo
  • Channel groups/IOs.
  • Acquisition timing.
  • Threshold tuning.
  • Noise filtering.
  • Key/slider basics.
Exercise:  Touch key demo
  • Flash erase/program.
  • True Data EEPROM use.
  • Simple wear-leveling.
  • OB: RDP/PCROP/BOR.
  • Reset cause logging.
Exercise:  EEPROM config
  • ROM bootloader ports.
  • DFU/UART/I²C options.
  • Boot pins & OB links.
  • IWDG vs WWDG basics.
  • Reset causes record.
Exercise:  IWDG + DFU try
  • Clocking proven (MCO).
  • I/O safe at boot/sleep.
  • Low-power numbers noted.
  • Comms error policy set.
  • UID/serial/CRC scheme.
Exercise:  Self-audit
Duration
3 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

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This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

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