FPGA
Programming and using programmable logic components
That is where the whole difficulty of learning lies. You are not writing a program, you are describing hardware. VHDL and SystemVerilog look like programming languages and are not: a loop is not a repetition in time but a replication in space, and a signal is not a variable. Beginners who approach VHDL as if it were C produce circuits that simulate correctly and fail to meet timing.
When an FPGA is the right answer
Three cases keep coming back: genuine parallelism, when dozens of channels must be handled simultaneously; deterministic latency, when a response is due within tens of nanoseconds, which no software interrupt can guarantee; and interfaces nobody sells, a proprietary protocol or a sensor with an unusual format.
Outside those cases a microcontroller stays simpler, cheaper and quicker to bring up. An FPGA is paid for in design time and in power consumption.
Describe, verify, integrate
Design is done in VHDL or SystemVerilog. SystemC comes in higher up, to explore an architecture before freezing the RTL.
Verification often weighs more than design itself. UVM is the industry standard methodology for building reusable testbenches: an unverified circuit is not a finished circuit.
Finally, most current FPGAs carry a processor, either hardened into the silicon like the Cortex-A9 in Zynq and Cyclone V devices, or synthesised into the fabric like MicroBlaze, Nios, Mico32 or a RISC-V core. Designing for these parts means splitting a function between software and hardware, and making the two talk to each other.
Our courses
VHDL Language Basics (V1) and Advanced VHDL for FPGA (V2) form the main path, from syntax to design methodology. SystemVerilog (U1) and UVM (U2) cover the verification side, Design with SystemC (V3) high-level modelling, and FPGA Optimization (V4) the work on performance and area. Programmable components fundamentals (V0) is the entry point for those starting from nothing.
On the device side, the courses follow the main vendors: AMD Zynq (HX5) and MicroBlaze (HX4), Cyclone V Cortex-A9 (ALT1) and Nios (ALT2), Lattice Mico32 (H1) and Diamond (H2), Microchip SmartFusion2 (MSP). RISC-V Architecture (RV1) covers the instruction set that has become hard to avoid for synthesised cores.
Hands-on work runs on real boards on site, and remotely on remotely accessible hardware or on the simulation tools we develop. A timing problem is only understood by watching it happen.