FPGA Nios (Nios II / Nios V) implementation Training | Ac6 Formation

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ALT2FPGA Nios (Nios II / Nios V) implementation

Objectives

  • Understand soft CPU concepts and Nios II / Nios V basics.
  • Build SoCs in Platform Designer (Avalon-MM/Stream, clock/reset).
  • Generate BSPs, bring up firmware, and debug via JTAG UART.
  • Use GPIO, timers, interrupts; add UART/SPI/I²C comms.
  • Configure SDRAM/Flash, linker placement, and boot options.
  • Stream data with DMA, compare CPU vs DMA throughput.
  • Run a small FreeRTOS app (tasks, ISRs, timing).
  • Create a custom Avalon-MM IP and control it from C.
  • Tune performance/power (caches, clocks, optimization).
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Practical activities (40-50% of duration)
    • Code examples, exercises and solutions.
    • Remote: one online Linux PC per trainee, with emulated or physical board as needed.
    • Face-to-face / on-site: one PC (one per two beyond six trainees), target board and install manual as needed.
  • Downloadable preconfigured VM to redo the labs afterwards.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the training.
  • Progress is assessed by the trainer through the practical exercises, and by quizzes for sections without exercises.
  • Each trainee receives a completion certificate.
  • If a prerequisite gap appears, alternative or additional training is offered.

Course Outline

  • Soft CPU idea (fabric vs hard CPU).
  • Nios II vs Nios V (high-level).
  • Interconnect: Avalon-MM / Stream.
  • Clock/reset domains.
  • Memory map concept.
Exercise:  Board & SoC tour
  • Quartus project basics.
  • Add IP, connect masters/slaves.
  • Clock source & reset bridges.
  • HDL generation & top-level.
  • Pin planner quick pass.
Exercise:  GPIO “blinky” SoC
  • BSP generation steps.
  • HAL vs bare-metal.
  • Linker script placement.
  • JTAG UART console.
  • Minimal driver calls.
Exercise:  Hello over JTAG
  • PIO input/output usage.
  • Interval timer basics.
  • Interrupt controller path.
  • Polling vs ISR patterns.
  • Simple debounce idea.
Exercise:  Button IRQ toggle
  • UART baud/format.
  • SPI mode (CPOL/CPHA).
  • I²C master ops.
  • Blocking vs IRQ/DMA.
  • Simple error checks.
Exercise:  Comms demo
  • On-chip RAM vs SDRAM.
  • SDRAM controller timing.
  • QSPI/Flash mapping.
  • Boot: JTAG, Flash.
  • Linker regions (.text/.data).
Exercise:  SDRAM placement
  • SG-DMA channels.
  • M2M, M2P, P2M paths.
  • Bursts and alignment.
  • Cache coherency notes.
  • Simple benchmarking.
Exercise:  DMA vs CPU copy
  • Tasks & priorities.
  • SysTick/timer tick.
  • Queues/semaphores.
  • ISR-safe APIs.
  • Stack/heap sizing.
Exercise:  Two-task demo
  • Component editor basics.
  • Slave regs and address map.
  • Read/Write stubs in HDL.
  • Export IRQ (optional).
  • Driver header in BSP.
Exercise:  LED pattern IP
  • ISA/toolchain note.
  • CSR/interrupt differences.
  • BSP template changes.
  • Rebuild flow in tools.
  • Compatibility tips.
Exercise:  Rebuild for Nios V
  • CPU vs DMA balance.
  • I/D cache choices.
  • Compiler flags (-O2/-O3).
  • Clock gating idea.
  • Simple profiling.
Exercise:  Cache on/off test
  • SignalTap capture.
  • UART boot logs.
  • Version/CRC tags.
  • Update script outline.
  • Factory test hooks.
Exercise:  SignalTap UART
Duration
3 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

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This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

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