Communication

Internet est de plus en plus omniprésent; il est maintenant inévitable dans les systèmes embarqués.

Every embedded system ends up moving bytes between two chips that were not designed together. The bus chosen for that job decides more than throughput: it decides latency, determinism, cable length, connector cost, and how much of the protocol you have to implement yourself.

Choosing a bus

CAN was built for vehicles and kept for anything that needs short messages, arbitration without a master, and tolerance to electrical noise. It is slow by modern standards and that is not the point.

USB is the answer when a host is present and the peripheral must be recognised without configuration. Its descriptor model and class system carry most of the complexity, and most USB bugs are enumeration bugs, not transfer bugs.

PCI Express is the choice for bandwidth inside a board or a chassis. It is a switched, packet-based fabric rather than a bus, which is precisely why treating it like a bus produces designs that do not scale.

MIL-STD-1553B belongs to avionics and defence: dual redundant, deterministic, command-response, and unchanged since 1978 because that stability is the requirement.

HDMI carries video, audio and control on one connector, with the licensing and content-protection constraints that come with it.

What the courses cover

New digital buses (I0) is the overview for teams that have to choose rather than implement. CAN bus (IA1) and MIL-STD 1553B (IA3) cover the deterministic side, the one where a missed deadline is a failure rather than a slowdown.

PCI 3.0 (IC1) and PCI Express 3.0 (IC4) cover the high-bandwidth path, from configuration space to link training. USB 2.0 (IP2) and USB 3.0 (IP3) cover the host and device sides, descriptors, classes and enumeration. HDMI 1.4a (IM1) covers the display link.

Each course works from the specification and from a protocol analyser, because a bus is understood by watching real traffic rather than by reading about it.

Ethernet won every market it entered, including the ones it was never meant for. It now carries factory automation, avionics, audio and measurement traffic that used to run on dedicated buses, and each of those uses asks something Ethernet did not originally provide: a bound on delay, or a shared notion of time.

From best effort to determinism

A switch introduces queuing, and queuing introduces jitter. A frame that normally crosses a network in fifty microseconds can take a millisecond when a burst arrives at the same port. For a web page nobody notices. For a motion control loop it is a fault.

That is where switch architecture stops being an implementation detail: store-and-forward against cut-through, buffer sizing, priority queues, and how a switch behaves when it is saturated.

IEEE 1588, Precision Time Protocol, solves the other half. It distributes a common clock across the network to sub-microsecond accuracy by measuring path delay rather than assuming it. It is what allows separate devices to sample, act or timestamp together, and it is the foundation of most time-sensitive networking.

What the courses cover

Ethernet and switching (N1) covers frames, switching, VLANs and the queuing behaviour that decides real latency. IEEE1588 Precise Time Protocol (N2) covers clock distribution, master selection, delay measurement and the hardware timestamping that makes accuracy possible. Ethernet 10 Gigabit (N3) covers the physical layers and the constraints that appear once a single link outruns the processor behind it.

Storage interfaces are where embedded designs quietly lose their performance. The flash device is fast, the controller is fast, and the measured throughput is a third of the figure on the datasheet. The gap is almost always in the interface: command queuing, transfer mode, alignment, or a power state the driver never leaves.

Three families, three sets of constraints

Serial ATA comes from the PC world and brought native command queuing with it. Its strength is mature tooling and predictable behaviour on rotating and solid-state media alike; its cost is a protocol stack heavier than most embedded systems need.

UFS was designed for mobile: full duplex, command queuing, low power states that matter as much as peak bandwidth. It is where high-end embedded storage has converged, and its power management is the part that most often surprises.

SD UHS-II keeps the removable card format and adds a differential interface underneath it. The compatibility rules between UHS-I and UHS-II hosts and cards are the part that produces the most support tickets.

What the courses cover

Serial ATA III (IS3), Universal Flash Storage UFS 2.0 (IS4) and SD UHS-II (IS5) each work from the specification down to the signalling, with the protocol traces that show where the throughput actually goes.