DDR4 / LPDDR4 Training | Ac6 Formation

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SDR1DDR4 / LPDDR4
This course covers both DDR4 and LPDDR4 SDRAM

OBJECTIVES

  • The course starts with a summary of DDR3/LPDDR3 specification.
  • Then DDR4 functional description is studied.
  • Differences between LPDDR4 and DDR4 are highlighted.
  • ZQ calibration and write levelling sequences are detailed.
  • The analog part is also described, particularly the tests to be performed using an oscilloscope.
  • An example of DDR4 controller provides an example of programming interface.

A more detailed course description is available on request at training@ac6-training.com
  • Knowledge of SDRAM.

  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the training.
  • Progress is assessed by quizzes at the end of sections.
  • Each trainee receives a completion certificate.
  • If a prerequisite gap appears, alternative or additional training is offered.

Course Outline

  • DDR3 organization
  • Burst chop mode
  • Initialization sequence, new RESET# signal
  • Dynamic ODT
  • ZQ calibration
  • Topologies, fly-by architecture
  • Write leveling
  • Low power modes
  • Power-up, initialization, and power-off
  • Mode Register Read command
  • Mode register definition
  • Timings for Activate, Read, Write, Precharge
  • Precharge & Auto Precharge clarification
  • Refresh command
  • Low power modes, self-refresh, partial array self refresh, power down, deep power down
  • Temperature sensor
  • CA training sequence
  • ZQ calibration, write levelling
  • Bank group vs Bank address
  • Alert output, CRC for write, Command Address parity
  • Reset and initialization procedure
  • Geardown mode
  • BL8 burst order with CRC enabled
  • Input clock frequency change
  • Write levelling
  • DQ training with MPR
  • Temperature controlled refresh modes
  • ZQ calibration
  • Vref training
  • Timings for Activate, Read, Write, Precharge
  • Read preamble training
  • Low power modes
  • Connectivity test mode
  • Pseudo-Open Drain termination
  • Pinout, addressing
  • 2-channel architecture
  • Power-up, initialization and power-off procedure
  • Mode register definition
  • Activation, read and write timing diagrams
  • LPDDR4 Data Mask (DM) and Data Bus Inversion (DBIdc) function
  • Low power modes
  • Vref training
  • Frequency set point update timing
  • Write levelling procedure
  • Read DQ calibration
  • ZQ calibration
  • On-Die Termination
  • Differential Input Cross Point Voltage
  • Slew rate requirements
  • LVSTL(Low Voltage Swing Terminated Logic) IO System
  • Temperature derating for AC timing
  • CA Rx voltage and timing
  • DQ Rx Voltage and Timing
  • Using an oscilloscope to qualify the interface
  • Example of NXP IP
  • Address multiplexing: bank interleaving vs page interleaving
  • PCB design considerations
  • ECC implementation
  • Tuning parameters
  • Initiating write leveling, hardware vs software calibration
  • Driver analog part configuration
  • Memory testing
Duration
2 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales