Processors

ARM cores sit inside most embedded designs shipping today, from a Cortex-M0+ running on a coin cell to a Cortex-A72 booting Linux. Performance is the visible difference. The exception model, the memory system and the security architecture differ enough that code written for one profile rarely moves to another unchanged.

The architecture itself keeps evolving. ARMv8-A brought 64-bit execution and exception levels, ARMv8-M brought TrustZone down to the microcontroller, and each generation adds to the debug and trace infrastructure. Knowing what the core guarantees, and what it leaves to software, is what separates firmware that works from firmware that works every time.

Our courses cover the Cortex-A, Cortex-R and Cortex-M families in depth: instruction sets, MMU and MPU, caches and coherency, exception handling, NEON and the FPU, the GIC, CoreSight debug, and the AMBA buses that tie a SoC together. Each one is built around lab work on real silicon.

STM32 covers an unusually wide range for a single microcontroller family, from the ultra-low-power L0 and U5 up to the H7 and the Linux-capable MP1 and MP2. The peripherals stay recognizable across families, which is what makes moving a design from one series to another realistic.

That consistency comes from the tooling as much as from the silicon. STM32CubeMX generates the clock tree and pin configuration, HAL and LL give two levels of driver abstraction, and the middleware layers bring FreeRTOS, LwIP, USB and file systems in without rewriting them. The work then shifts to what actually matters: clock design, DMA, low-power strategy and boot configuration.

Our courses cover the families in use today, series by series, along with the peripherals shared across them, TrustZone-M security on the L5, H5 and U5, the wireless parts, and the complete case of an STM32 running FreeRTOS and a TCP/IP stack at the same time.

NXP spans the whole embedded range, from the LPC and Kinetis microcontrollers up to the i.MX application processors and the QorIQ communications platforms. They share little beyond the vendor name: a Kinetis boots in microseconds, a T4240 carries twelve cores and a packet processing engine.

The larger devices are where the difficulty sits. QorIQ parts pair Power Architecture or ARM cores with the Data Path Acceleration Architecture, where frames are handled by dedicated managers rather than by software. Getting throughput out of them means understanding the Frame, Queue and Buffer Managers, the CoreNet fabric and the PAMU, not just the core.

Our courses cover the Kinetis and LPC microcontrollers, the i.MX6 and i.MX8m application processors, and the QorIQ line in detail, including the e5500 and e6500 cores, DPAA, secure boot and the integrated peripherals. Hardware implementation and software development are both covered.

Texas Instruments builds embedded processors that span single Cortex-M microcontrollers up to the multicore KeyStone devices combining ARM cores with C66x DSPs. Each family comes with its own memory architecture, interconnect and boot sequence.

Our courses cover the Cortex-M4 platform with TI-RTOS and the KeyStone II architecture: core and DSP subsystems, Multicore Navigator, memory hierarchy, peripherals and boot modes. Both hardware implementation and software development are covered, with lab work on real boards.

On KeyStone the difficulty is the interconnect, not the cores: Multicore Navigator queues, packet DMA, and the memory hierarchy across L1, L2 and the shared MSMC. On the Cortex-M side it is TI-RTOS, its scheduler and its driver model. Both are covered with lab work on real boards.

Silicon Labs Series 2 wireless SoCs put a Cortex-M33 with TrustZone next to a radio and a dedicated security subsystem. The EFR32MG2x family targets connected products that have to prove their firmware is authentic and stays that way through years of field updates.

Our course covers that security stack end to end: TrustZone partitioning, the Security Attribution Unit, secure boot with the RTSL root of trust, Secure Vault key storage, Gecko Bootloader configuration, secure debug lockdown and OTA update with anti-rollback.

The detail matters here because the chain breaks at its weakest link: fuse and OTP programming that cannot be undone, key provisioning during manufacturing, the anti-rollback counters that stop a downgrade attack, and debug lockdown that has to leave a way to diagnose returns. The course covers each step in order.