VFP programming Training | Ac6 Formation

ac6-formation, un département d'Ac6 SAS
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ac6 ac6-formation Processors ARM Cores VFP programming
RC0VFP programming
This course explains how to use VFP instructions to boost multimedia algorithms

Objectives

  • This course has been designed for programmers wanting to develop algorithm based on hardware floating point calculations.
  • Each instruction family is detailed, first at assembly level, and then at C level using macros.
  • Several tricky usage of vector instructions are provided.
  • The underlying cache operation as well as preload mechanisms (instruction and hardware prefetch) are detailed to explain how a processing can be pipelined .
  • The course shows how DSP typical algorithms such as FIR and FFT can be vectorized and then optimized to be executed on VFP unit.

  • THIS COURSE IS PROPOSED EITHER AS AN INSTRUCTOR-LED COURSE OR AS E-LEARNING.

  • ACSYS has developed an optimized VFP based FFT coded in assembler language
    • performance for 1024 complex floating point single precision samples is 220_000 core clock cycles (ARM11)
    • for any information contact formation@ac6-formation.com
Labs are run under RVDS
A more detailed course description is available on request at formation@ac6-formation.com
  • Knowledge of 4T / V5TE instruction set.
  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the training.
  • Progress is assessed by quizzes at the end of sections.
  • Each trainee receives a completion certificate.
  • If a prerequisite gap appears, alternative or additional training is offered.

Course Outline

  • Floating point number coding
  • Denormalized numbers
  • NaN utilization
  • Rounding modess
  • VFP FPEXC register
  • Register bank, D registers, S registers
  • Instruction coding, either ARM or Thumb-2
  • Related system registers
  • Alignment issues
  • Context switching
  • Length / Stride combinations
  • Scalar operations
  • Vector operations
  • Mixed operations
  • Addressing modes
  • Floating point load / store
  • Floating point load / store multiple
  • Processor acceleration mechanisms: store merging buffers
  • Add / subtract / absolute value instructions
  • Multiply and multiply accumulate instructions
  • Divide instruction
  • Square root instruction
  • Compare instructions
  • Integer to FP and FP to convert instructions
  • FIR filter
    • Converting the scalar algorithm into a vector algorithm
    • Finding the VFP instructions to encode the vector algorithm
    • Optimizing the code
  • FFT (DFT)
    • Converting the scalar algorithm into a vector algorithm, understanding how circle properties can be used to process 4 angles concurrently
    • Finding the VFP instructions to encode the vector algorithm
    • Optimizing the code
More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales