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ac6 › ac6-formation › Programming › FPGA › Xilinx - Spartan-6 / Virtex-6 Integrated PCI Express Block
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Xilinx - Spartan-6 / Virtex-6 Integrated PCI Express Block

This course covers the implementation of the Xilinx PCIe block.

Objectives

  • An introduction to PCI Express protocol is done at the beginning to be able later to understand the operation of the back-end bus.
  • The course details the parameterizing of the PCI Express core.
  • User interfaces are deeply detailed.
  • Management of errors and interrupts is studied through examples.
  • Guidelines to design the user logic are provided.
  • The course targets hard PCI Express cores in the Virtex-6 and Spartan-6 FPGAs.

Xilinx software (ISE) is used to synthesize and implement practical examples, Mentor Graphics ModelSim is used for simulation.
A more detailed course description is available on request at formation@ac6-formation.com
  • Good knowledge of PCIe gen2 protocol, see our course reference IC4 - PCI Express 3.0 course
  • Good knowledge of VHDL.
  • Experience with simulation tools such as Mentor Graphics ModelSim.
  • Basic knowledge of Xilinx ISE software.

  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the course starts, against the prerequisites published on this page.
  • Throughout the course, learning is assessed continuously: end-of-section quizzes and direct observation by the trainer.
  • At the end of the course, each participant receives a training completion certificate.

Course Outline

  • Introduction to PCI Express
  • Transactions types and categories
  • Address Space Map and Configuration Space
  • PCI type0 basics, PCI express capability structure
  • Selecting link speed and width
  • Address decoding logic, BAR registers setting
  • TLP buffer sizing
  • Power management configuration
  • Optional capability structures
  • Identifying simulation points
  • Simulation Methods
  • Building TestBench
  • Clocking and reset
  • Common Transaction Interface Signals
  • Cut-through vs Store & Forward operation
  • Migrating to the integrated block for PCI Express v2.x from v1.x
  • AXI interface signals description
  • Managing control flow information to optimize the user logic
  • PIO example description
  • Endpoint application and PCI Express core connection
  • Local Link or AXI interface
  • Accessing configuration space from user logic
  • Chipscope Pro Description
  • Compliance Testing
  • Tracking the transitions in the LTSSM (Virtex-6)
  • Dynamic reconfiguration (Virtex-6)
  • PCIe Error management, related registers
  • Introduction to legacy interrupts, MSI and MSI-X
  • Collaborating with PCIe block to generate error messages
  • Triggering interrupts, MSI or MSI-X from user logic
  • Explaining the benefits of MSI / MSI-X with respect to legacy interrupts
Duration
2 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

Pricing

Courses are quoted individually, with no list price. The price depends on the duration, the number of participants, the delivery mode and the technical resources provided.

For more information on our pricing, see more.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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