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DSP568XX implementation

This course covers the 568XX 16-bit DSP NXP family

Objectives

  • The course explains how to design a 56807 based board.
  • Optimized coding examples are described.
  • A generic interrupt handler is introduced.
  • The course focuses on motor driving.
  • Practical exercices are executed on a 56807 board.

  • This course has been delivered several times to companies developing electric engines.
A lot of programming examples have been developed by ACSYS to explain how to write optimized code.
•  They have been developed with CodeWarrior compiler and are executed under CodeWarrior debugger.
A more detailed course description is available on request at formation@ac6-formation.com
  • Basic knowledge about signal processing and motor control.
  • Knowledge of CAN bus is recommended, see our course reference CAN bus, reference IA1 - CAN bus course

  • Theoretical course
    • PDF material in English (printed for face-to-face); online over Teams.
    • Trainer assistance throughout.
  • Each session starts with a trainee check-in.
  • Any embedded systems engineer or technician with the above prerequisites.
  • Prerequisites are checked before the course starts, against the prerequisites published on this page.
  • Throughout the course, learning is assessed continuously: end-of-section quizzes and direct observation by the trainer.
  • At the end of the course, each participant receives a training completion certificate.

Course Outline

  • Arithmetic processing of real-time signals
  • Filtering, convolution, correlation
  • Modified dual Harvard architecture
  • DSP 568XX family introduction, compatibility with 5600X DSPs
  • Introduction of motor types
  • Core buses
  • Processing states
  • Reset, low voltage, stop and wait operations
  • 56807 mapping
  • The Data ALU
  • The Address Generation Unit
  • The Program Control Unit
  • The instruction set
  • C-to-assembly interface
  • Software techniques
  • Exception management
  • The interrupt routing performed by the ICTN
  • The debugging support
  • JTAG use to access the OnCE
  • The embedded flash memory
  • Program sequence
  • Erase sequence
  • On chip clock synthesis
  • Wait state X data memory
  • Wait state program memory
  • Timer module pinout
  • Operating modes
  • OFLAG output signal
  • Timing, pipelining
  • Conversion sequence definition
  • Synchronization to the PWM
  • Optional sample correction
  • Quadrature decoders pinout
  • Configurable digital filters
  • Watchdog timer implementation
  • Independent or complementary channel operation
  • Deadtime generators
  • IFault protection
  • SCI block diagram, IO signals
  • Asynchronous vs synchronous operation modes
  • Baud rate selection
  • Bootstrap loading from the SCI
  • Asynchronous transmit and receive sequences
  • SPI synchronous communications basics
  • Master vs slave selection
  • Polarity selection
  • The MSCAN controllers
  • Message buffers structure
  • ID bit masking
  • Arbitration
  • Timing and synchronization
  • Error management
Duration
3 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

Pricing

Courses are quoted individually, with no list price. The price depends on the duration, the number of participants, the delivery mode and the technical resources provided.

For more information on our pricing, see more.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 27 June 2026

Booking one of our trainings is subject to our General Terms of Sales

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