| IN1 | Pentium-M implementation |
This course covers Intel Pentium-M X86 low power processor
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Objectives
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- Theoretical course
- PDF course material (in English) supplemented by a printed version for face-to-face courses.
- Online courses are dispensed using the Teams video-conferencing system.
- The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
- At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
- Any embedded systems engineer or technician with the above prerequisites.
- The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
- Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
- At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
- In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
- Overview, implementation of IA-32 architecture
- Operation modes
- X86 fundamentals
- Privilege levels
- Segments
- Accessing High Memory Area
- Flat mode
- Virtual memory
- X86 virtual mode
- Task management
- Segment descriptors : GDT vs LDT
- Code segment, conforming vs non-conforming segments
- Call gate utilization
- Data segment
- Task State Segment [TSS]
- Task gate
- Task switching
- I/O space protection
- 386 page translation
- PDE and PTE format
- Privilege level checking
- Pentium 4-MB pages
- PAE-36
- PSE-36
- VMM requirements
- Video frame buffer virtualization
- Memory Type and Range Registers
- Page attribute table
- Vector table
- Priority between exceptions
- Exception management in real mode
- Exception management in protected mode
- Interrupt and trap gates
- Exception return
- Exception management in VM86 mode
- Acceleration mechanisms : sysenter and sysexit instructions
- Interrupt management in SMP platforms
- Local interrupts
- Interrupt management sequence
- IPI generation and reception
- Message Signaled Interrupts
- MSI utilization in Pentium platforms
- Pentium-II power management, state machine
- Pentium-M power management, deeper sleep new state
- SpeedStep technology
- System Management Mode
- Interrupt management when SMM is active
- Transition to Power-Down
- Hardware configuration
- Processor state after a reset
- Selecting the bootstrap processor
- Configuring Auxiliary processors
- Microcode update
- Detail of the 11 stages
- Hyper-threading, Pentium-4 implementation
- CPU resource utilization
- Instruction execution steps
- L2 cache organization
- Hit under miss
- Miss under miss
- Squashing
- Mixing 16-bit and 32-bit codes
- I/O space access instructions
- Addressing modes
- SSE instructions, register set
Duration
3 days
Cost
1750 € HT
Calendar
To book a training session or for more information, please contact us on info@ac6-training.com.
Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.
You can also fill and send us the
registration form
This course can be provided either remotely, in our Paris training center or, worldwide, on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 2 working days before the course start (1 week for face-to-face courses).
Booking one of our trainings is subject to our
General Terms of Sales
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