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M5 440GP/GX implementation

This course covers AMCC 440GP and 440GX processors

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Objectives
  • The course explains how to design a 440GX board.
  • DDR SDRAM operation is described in order to understand the parameterizing of the memory controller.
  • Book E PowerPC architecture is studied, especially the MMU.
  • The course provides examples of internal peripherals software drivers.
  • Gigabit Ethernet controller and TCP/IP Acceleration Hardware are viewed in detail.
  • The training focusses on data path between PCI-X bus and internal PLB bus.

  • This course has been delivered several times to companies developing embedded equipments (multimedia systems and avionics systems).

  • A chapter on Linux porting can be appended on request.
Labs are compiled with Diab Data compiler and run under Lauterbach debugger.
A more detailed course description is available on request at formation@ac6-formation.com
  • Experience of a 32 bit processor or DSP is mandatory.
  • Knowledge of PCI-X bus is recommended, see our course reference IC3 - PCI-X 2.0 course.
  • Knowledge of Gigabit Ethernet is recommended, see our course reference N1 - Ethernet and switching course.
  • Theoretical course
    • PDF course material (in English) supplemented by a printed version for face-to-face courses.
    • Online courses are dispensed using the Teams video-conferencing system.
    • The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
  • At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
  • Any embedded systems engineer or technician with the above prerequisites.
  • The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
  • Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
  • At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
    • In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.

Course Outline

  • Block diagram
  • Internal concurrent transfers examples
  • Hardware introduction
  • 440GP/GX mapping
  • Programming model
  • Comparison between 440GP and 440GX
  • PLB arbiter, OPB arbiter and PLB-to-OPB bridge configuration
  • Bus errors recovering from syndrome registers
  • PLB performance monitor
  • Pipeline operation
  • Internal caches
  • CCR0 register
  • Speculative loads, storage ordering and synchronization : msync & mbar instructions
  • MMU
  • Branch instructions
  • Addressing modes, load & store instructions
  • Integer instructions
  • 16-bit mac instructions
  • Exception management
  • Core timers
  • PowerPC EABI
  • JTAG emulator use
  • Real time trace
  • Clocks synthesizer
  • Low power modes
  • Reset
  • Boot routine example
  • IIC bootstrap controller
  • Interrupt masking and acknowledgement e
  • Critical interrupt handlers using vectorization
  • Write-through cache, understanding the data and instruction path
  • Performance monitor
  • SRAM utilization - base address definition
  • Access errors
  • DDR-SDRAM operation
  • Jedec specification basics
  • Hardware interface
  • Bank activation, read, write and precharge timing diagrams
  • ECC error correction
  • Initial configuration following Power-on-Reset
  • Address decode
  • Timing parameters programming
  • External bus pinout, driver enables
  • Dynamic bus sizing
  • Address decoding
  • Timing parameters initialization
  • Device-paced transfers
  • External bus master interface
  • Data flows
  • Inbound an outbound transactions handling
  • Address mappings
  • Synchronization between CPUs : the MSI registers
  • I2O messaging unit, passing messages between processor nodes
  • Boot modes, initialization / Reset sequence
  • The buffered transfer mode
  • Related signals
  • Channels bus priority
  • Data packing / unpacking
  • Buffers chaining
  • Frame format with and without VLAN option
  • Ethernet controller organization
  • PHY interface
  • Hash table restrictions
  • Buffer descriptors management
  • Transmit sequence
  • Receive sequence
  • Checksum management
  • TCP segmentation in the transmit path
  • VLAN tagged frames
  • The UART frame : break, idle, start, stop
  • Transmission and reception FIFOs use
  • Flow control signals management
  • IIC protocol basics
  • Transfer timing diagrams
  • Transmit and receive sequences
Duration
5 days
Cost
2100 € HT
Calendar
Session calendar

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the Adobe PDF format file registration form

This course can be provided either remotely, in our Paris training center or, worldwide, on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 2 working days before the course start (1 week for face-to-face courses).

Last update of course schedule: 19 February 2023

Booking one of our trainings is subject to our Adobe PDF format file General Terms of Sales

 

Ac6 SARL
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Last site update: Monday 29 April, 2024 at 15:33:05 CEST (Europe/Berlin)
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