ac6-formation, an Acsys department
Formation Marvell bridges - MARVELL MV64560 implementation
View the site in Français Site displayed in English (USA) View the site in English (GB)
You are here: ac6 > ac6-formation > Marvell bridges > MARVELL MV64560 implementation

MV2 MARVELL MV64560 implementation

This course covers Marvell Discovery V devices

Objectives
bullet_jaune_1 The course describes the MV64560 internal data paths.
bullet_jaune_1 The course explains how the host PowerPC and a CPU connected to PCI-X can synchronize to each other through the message unit.
bullet_jaune_1 Operation of the PCI Express interface is detailed in Root Complex mode as well as in Endpoint mode.
bullet_jaune_1 A long introduction to DDR SDRAM is done prior to describe the DDR SDRAM controller operation.
bullet_jaune_1 The course focuses on the hardware implementation of the DDR SDRAM.
bullet_jaune_1 The training explains how to implement chained DMA transfers, by using either IDMA channels or XOR engines.
bullet_jaune_1 The course highlights the possible optimizations that can be implemented to boost the performance of the Ethernet controller.
bullet_jaune_1 This course has been delivered several times to companies developing defence and avionics systems.
A more detailed course description is available on request at info@ac6-formation.com
Pre-requisites
bullet_jaune_2 Knowledge of PowerPC 60X / MPX bus. See our courses on Freescale and IBM Microelectronics PowerPCs.
Related courses
bullet_jaune_2 Ethernet and switching, reference N1
bullet_jaune_2 PCI express, reference IC4
bullet_jaune_2 USB Full Speed High Speed and USB On-The-Go, reference IP2
Outline
OVERVIEW
bullet_jaune_2 5-bus architecture, organization of a board based on MV64560
bullet_jaune_2 Frequency domains, fast path between CPU and SRAM / SDRAM
bullet_jaune_2 Internal crossbar
bullet_jaune_2 Master de-mux programming, address decode windows
bullet_jaune_2 Slave mux programming, pizza arbiters operation
bullet_jaune_2 Compatibility with MV64460
CPU INTERFACE
bullet_jaune_2 CPU address space decoding
bullet_jaune_2 Protection windows
bullet_jaune_2 Arbitration, multi-processor operation
bullet_jaune_2 CPU slave operation
bullet_jaune_2 CPU master operation (60X mode)
bullet_jaune_2 Cache coherency
bullet_jaune_2 Deadlock avoidance
DDR1/2 INTERFACE
bullet_jaune_2 Introduction to DDR SDRAM from Jedec specification
bullet_jaune_2 Differences between DDR1 and DDR2
bullet_jaune_2 DDR2 on-die terminations
bullet_jaune_2 Initialization sequence
bullet_jaune_2 DDR1/2 SDRAM controller
bullet_jaune_2 Page management
bullet_jaune_2 Transaction ordering
bullet_jaune_2 Cache coherency
bullet_jaune_2 ECC and read-modify-write transactions
bullet_jaune_2 Low power modes
DEVICE CONTROLLER
bullet_jaune_2 Functional description
bullet_jaune_2 Address and data multiplexing
bullet_jaune_2 Connecting 8/16 bit devices
bullet_jaune_2 External acknowledgement
bullet_jaune_2 Pack / unpack and burst support
bullet_jaune_2 NAND flash support, boot from NAND flash
PCI INTERFACE
bullet_jaune_2 PCI bus arbitration
bullet_jaune_2 Master operation in PCI and PCI-X mode
bullet_jaune_2 Target operation in PCI and PCI-X mode
bullet_jaune_2 PCI-to-PCI configuration transactions
bullet_jaune_2 Address decoding
PCI-EXPRESS x4 INTERFACE
bullet_jaune_2 Integrated low power SERDES PHY
bullet_jaune_2 x1, x4 link
bullet_jaune_2 Operating as either Root Complex or Endpoint
bullet_jaune_2 Link initialization
bullet_jaune_2 Arbitration and ordering
bullet_jaune_2 Messaging unit
GENERAL PURPOSE INPUT/ OUTPUT PINS
bullet_jaune_2 GPIO port, functional description
bullet_jaune_2 Interrupt request inputs
bullet_jaune_2 Multi Purpose Pin multiplexing
INTERRUPT CONTROLLERS AND TIMERS
bullet_jaune_2 Timers / counters
bullet_jaune_2 Interrupt controller functional description
bullet_jaune_2 Priority mechanism
TWSI CONTROLLER AND RESET
bullet_jaune_2 I2C protocol basics
bullet_jaune_2 TWSI controller functional description
bullet_jaune_2 Master write sequence, master read sequence
bullet_jaune_2 Slave write sequence, slave read sequence
bullet_jaune_2 Reset pins and configuration
bullet_jaune_2 Serial ROM initialization
bullet_jaune_2 Requirement for an external Central Resource CPLD
IDMA CHANNELS
bullet_jaune_2 IDMA address decoding
bullet_jaune_2 Target unit and attributes programming
bullet_jaune_2 Normal mode vs chained mode
bullet_jaune_2 Transfer descriptors, descriptor ownership
bullet_jaune_2 DMA interrupts
XOR ENGINES
bullet_jaune_2 State machine : Active, Inactive and Paused states
bullet_jaune_2 XOR operation mode
bullet_jaune_2 CRC32 operation mode
bullet_jaune_2 DMA operation mode
bullet_jaune_2 Memory Initialization operation mode
bullet_jaune_2 ECC error cleanup operation mode
bullet_jaune_2 XOR Engines interrupts
16550 COMPATIBLE UARTs
bullet_jaune_2 FIFO mode
bullet_jaune_2 Flow control
bullet_jaune_2 Transmit sequence
bullet_jaune_2 Receive sequence
USB2.0 PORTS
bullet_jaune_2 Address decoding
bullet_jaune_2 Integrated PHY
bullet_jaune_2 USB host operation, EHCI specification support
bullet_jaune_2 USB device operation, Endpoint configuration
GIGABIT ETHERNET CONTROLLERS
bullet_jaune_2 Interface to the PHY
bullet_jaune_2 SGMII support
bullet_jaune_2 Dedicated DMA
bullet_jaune_2 Transmit weighted round-robin arbitration
bullet_jaune_2 Backpressure mode
bullet_jaune_2 Transmit and receive sequences
bullet_jaune_2 Management interface
bullet_jaune_2 Synchronous FIFO interface
 
Duration Cost Calendar
4 days 1950 € Session calendar
 

Acsys SARL
webmaster@ac6-formation.com
Last site update: Tue 22 May 2012 10:50:29 AM CEST