STR10STM32F7
This course descirbe the STM32F7 architecture and practical examples
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Objectives
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- Theoretical course
- PDF course material (in English) supplemented by a printed version for face-to-face courses.
- Online courses are dispensed using the Teams video-conferencing system.
- The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
- Practical activities
- Practical activities represent from 40% to 50% of course duration.
- Code examples, exercises and solutions
- For remote trainings:
- One Online Linux PC per trainee for the practical activities.
- The trainer has access to trainees' Online PCs for technical and pedagogical assistance.
- QEMU Emulated board or physical board connected to the online PC (depending on the course).
- Some Labs may be completed between sessions and are checked by the trainer on the next session.
- For face-to-face trainings:
- One PC (Linux ou Windows) for the practical activities with, if appropriate, a target board.
- One PC for two trainees when there are more than 6 trainees.
- For onsite trainings:
- An installation and test manual is provided to allow preinstallation of the needed software.
- The trainer come with target boards if needed during the practical activities (and bring them back at the end of the course).
- Downloadable preconfigured virtual machine for post-course practical activities
- At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
- Any embedded systems engineer or technician with the above prerequisites.
- The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
- Trainee progress is assessed in two different ways, depending on the course:
- For courses lending themselves to practical exercises, the results of the exercises are checked by the trainer while, if necessary, helping trainees to carry them out by providing additional details.
- Quizzes are offered at the end of sections that do not include practical exercises to verifythat the trainees have assimilated the points presented
- At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
- In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
- Programmer’s model (R0–R15, xPSR)
- MSP/PSP, exception entry/return
- Pipeline & branch prediction
- I-Cache / D-Cache basics
- ITCM / DTCM usage
- FPU
- SIMD
- MPU regions (intro)
| Exercise: | Core & cache sanity | |
- AXI matrix, AHB/APB bridges
- Flash, SRAM1/2/3 layout
- ITCM/DTCM address zones
- Peripheral regions (APB1/APB2)
- QSPI mapped memory (XIP)
- UID / Flash size registers
- HSI/HSE/PLL sources
- PLL M/N/P/Q settings
- AHB/APB1/APB2 prescalers
- OverDrive (216 MHz) (variants)
- Boot pins, Option Bytes
- Clock security (CSS)
| Exercise: | Clock profiles | |
- Modes: PP/OD, pulls
- Speed/drive strength
- AF mapping rules
- EXTI lines & priorities
- Debounce choices
- Safe I/O at reset
| Exercise: | GPIO / EXTI | |
- PWM edge/center
- One-pulse mode
- Input capture
- Encoder interface
- Master/Slave triggers
- LPTIM (if present)
- Break/dead-time (adv)
| Exercise: | PWM + capture | |
- DMA1/DMA2 streams/channels
- FIFO & burst modes
- Mem2mem / P2M / M2P
- Circular/HT/TC/TE IRQs
- Coherency with D-Cache
- DMA2D blit (variants)
| Exercise: | UART RX DMA ring | |
- ADC1..3 (12-bit)
- Regular vs injected
- Sampling time, ranks
- Timer-triggered ADC
- DMA coupling
- DAC dual channel
| Exercise: | ADC + DMA stream | |
- 8/9-bit, parity/stop
- Oversampling 16/8
- Blocking / IRQ / DMA
- RX ring with idle detect
- Error handling (FE/ORE)
- Wake from Stop (if used)
| Exercise: | Robust UART | |
- SPI mode CPOL/CPHA
- Data sizes, NSS
- Full-duplex DMA
- I²S basic audio path
- SAI blocks (TX/RX)
| Exercise: | SPI loopback DMA | |
- Sm/Fm/Fm+ speeds
- Addr 7/10-bit
- Filters (analog/digital)
- Timeouts & bus-clear
- Clock stretching
- Error recovery
- SDMMC 1/2
- FatFS basics
- QSPI XIP mapping
- FMC SDRAM/NOR/NAND
- Cache maintenance (SCB)
- Buffer alignment rules
| Exercise: | SD card + FatFS | |
- MII/RMII PHY link
- Descriptors & rings
- DMA settings
- LwIP minimal config
- Link/ARP/ping tests
| Exercise: | Eth bring-up | |
- Device/Host roles
- FS internal / HS via ULPI
- EP/FIFO sizing
- CDC/MSC quick paths
- Low-power suspend/resume
- I-Cache enable/invalidate
- D-Cache clean/invalidate
- Cache pitfalls with DMA
- ITCM code placement
- DTCM data placement
- MPU regions & attrs
| Exercise: | TCM vs AXI bench | |
- LTDC layers/timings
- Framebuffer in SDRAM
- DMA2D color fill/blit
- DCMI capture basics
- Simple UI primitives
| Exercise: | Color-bar FB | |
- Sleep/Stop/Standby
- OverDrive vs Stop trade-off
- Wake sources (EXTI/RTC)
- Clock gating checklist
- Retention notes
| Exercise: | Stop + wake | |
- CRC unit
- RNG TRNG
- HASH (SHA-1/256)
- CRYP (AES/TDES)
- Key storage basics
| Exercise: | AES or CRC check | |
- Boot ROM interfaces
- OB: RDP/WRP/BOR
- Dual-bank (variants)
- QSPI/SD boot ideas
- Watchdogs IWDG/WWDG
- Reset causes log
| Exercise: | IWDG + reset log | |
- Clocking & wait-states
- Cache/MPU policy
- External memory proof
- Comms robustness list
- UID/serial/versioning
- Error counters & logs
| Exercise: | Self-audit sheet | |
More
To book a training session or for more information, please contact us on info@ac6-training.com.
Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.
You can also fill and send us the registration form
This course can be provided either remotely, in our Paris training center or worldwide on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.
Last update of course schedule: 3 October 2024
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