H1Lattice Mico32 FPGA embedded processor
Implementing and programming a processor core in an FPGA
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Goals
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- A Windows PC per two trainees
- The Lattice Diamond FPGA programming tool
- The MSB tool for creating Mico32 Open Source platform
- The software development environment (based on Eclipse)
- The installation of the platform on uClinux and uC/OSII
- A Lattice ECP2 target board
- Printed handouts of the course slides
- Labs presentation and solutions
- Basic understanding of processor architecture
- Good knowledge of VHDL programming (V1 - VHDL Language Basics course level)
- Knowledge of embedded programming in C (if possible L2 - C language for Embedded MCUs course level)
- For a good understanding of installing uClinux it is desirable to have a basic knowledge of
- Embedded Linux (see D1 - Embedded Linux with Buildroot and Yocto course) to understand the uClinux boot process
- Linux programming (see D0 - Linux user mode programming course) for Linux programming exercises
- Any embedded systems engineer or technician with the above prerequisites.
- The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
- Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
- At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
- In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
- Definition of the platform
- Creation of the physical architecture of the system
- Choice of characteristics and design
- VHDL code generation of the platform
- Implementation of the platform
- Verification of the platform
- Creation of the bitstream for programming the FPGA
- Programming the platform
- Choice of software infrastructure
- Programming in C and assembler
- Selecting core options
- Caches
- Interrupt controller
- Memory selection and configuration
- Internal RAM and ROM
- External flash, serial and parallel
- SRAM and external DDRAM
- Choosing and configuring devices
- GPIOs
- Timer
- UART, SPI, I2C
- Ethernet
- DMA Controller
- Bus arbitration strategies
- Private or shared busses
- Static or dynamic arbitration
- Configuring the platform
- Connection of peripheral bussesto
- Connection of peripheral interrupt controllers and DMA
- Choice of addresses and interrupts
- Checking the consistency of the platform
- VHDL code generation of the platform
- Behavioral Simulation
- Using the testbench generated by the MSB
- Synthesis according to the chosen FPGA
- Definition of inputs / outputs
- Placement
- Routing
- After routing simulation
- Checking timings
- Control processing speed
- FPGA programming
- Generating the bitstream
- Transfer to the target
- C programming
- The Eclipse-based programming environment
- Program Runtime Environment
- Programming and code generation constraints
- Linker memory definition
- Simulation on the development station
- Using the MICO32 platform simulator
- Transfer to the target
- Cross debugging
- Use of GDB to cross-debug the program on the target
- Installing micrium uC/OSII on the target platform
- Specific platform requirements for uC/OSII
- Configuration uC/OSII to fit the platform
- Create a simple program
- Recompile
- Transfer on the target
- Cross-debug
- Installing u-boot on the target
- Specific platform requirements for u-boot and uClinux
- Configuring u-boot to fit the platform
- Recompile u-boot
- Transfer on the target
- Auto-test of the platform by u-boot
- Installing uClinux
- Configure the Linux kernel
- Choice of boot parameters
- Creation of programs for uClinux
- Compilation under Eclipse for uClinux
- Cross-debug
- The Wishbone bus
- Bus topology and signals
- Master interfaces
- Slave interfaces
- Defining custom input/output components
- Creation of the component VHDL code
- Integration into the Mico System Builder
- Creation of a platform including the new component
- Use of custom components in software
- Creating a program using acomponent
- Notion of driver
- Deployment of bitstreams in SPI flash
- Using the JTAG port to program the flash
- Deployment of tested code in parallel flash
- Creation of the flash programming infrastructure
- Reconfiguration of the application for execution from flash
- Deployment of an integrated application
- Deployment of a complete uClinux image
More
To book a training session or for more information, please contact us on info@ac6-training.com.
Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.
You can also fill and send us the registration form
This course can be provided either remotely, in our Paris training center or worldwide on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.
Last update of course schedule: 23 February 2026
Booking one of our trainings is subject to our General Terms of Sales
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