STR15STM32G4
This course descirbe the STM32G4 architecture and practical examples
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Objectives
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- Theoretical course
- PDF course material (in English) supplemented by a printed version for face-to-face courses.
- Online courses are dispensed using the Teams video-conferencing system.
- The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
- Practical activities
- Practical activities represent from 40% to 50% of course duration.
- Code examples, exercises and solutions
- For remote trainings:
- One Online Linux PC per trainee for the practical activities.
- The trainer has access to trainees' Online PCs for technical and pedagogical assistance.
- QEMU Emulated board or physical board connected to the online PC (depending on the course).
- Some Labs may be completed between sessions and are checked by the trainer on the next session.
- For face-to-face trainings:
- One PC (Linux ou Windows) for the practical activities with, if appropriate, a target board.
- One PC for two trainees when there are more than 6 trainees.
- For onsite trainings:
- An installation and test manual is provided to allow preinstallation of the needed software.
- The trainer come with target boards if needed during the practical activities (and bring them back at the end of the course).
- Downloadable preconfigured virtual machine for post-course practical activities
- At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
- Any embedded systems engineer or technician with the above prerequisites.
- The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
- Trainee progress is assessed in two different ways, depending on the course:
- For courses lending themselves to practical exercises, the results of the exercises are checked by the trainer while, if necessary, helping trainees to carry them out by providing additional details.
- Quizzes are offered at the end of sections that do not include practical exercises to verifythat the trainees have assimilated the points presented
- At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
- In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
- Core architecture
- Programmer's model
- Exceptions, NVIC priorities.
- DSP instructions (SIMD/MACC).
- FPU single-precision.
- WFI/WFE basics.
| Exercise: | Exception Management | |
| Exercise: | SIMD demo | |
- Bus matrix AHB/APB.
- Flash/SRAM regions.
- Peripheral address map.
- UID / Flash size regs.
- Option bytes (overview).
| Exercise: | Map & IDs | |
- HSI/HSE/PLL sources.
- PLLs
- SYSCLK mux, AHB/APB prescalers.
- Kernel clocks (CCIPR).
- MCO output, CSS.
| Exercise: | Clock profiles | |
- Modes: PP/OD, pulls.
- Speed/drive strength.
- AF mapping rules.
- EXTI lines and priorities.
- Safe I/O at reset.
| Exercise: | GPIO / EXTI | |
- PWM edge/center.
- Input capture, one-pulse.
- Encoder interface.
- Master/slave triggers.
- LPTIM for tickless.
| Exercise: | PWM + capture | |
- Stream/channel mapping.
- Circular vs normal.
- HT/TC/TE IRQs.
- Throughput vs latency.
- Restart on errors.
| Exercise: | UART RX ring | |
- Resolution & sampling time.
- Oversampling & alignment.
- Timer/HRTIM triggers.
- DMA continuous/circular.
- Analog watchdog.
| Exercise: | ADC + DMA stream | |
- OPAMP PGA modes.
- COMP thresholds/hysteresis.
- Routing to timers/EXTI.
- DAC 12-bit with S&H.
| Exercise: | Signal chain | |
- CORDIC trig/vectoring.
- FMAC FIR/IIR blocks.
- Stream I/O with DMA.
- Latency vs CPU DSP.
| Exercise: | CORDIC vs SW | |
- Timer units & outputs.
- Dead-time & break inputs.
- Complementary PWM pairs.
- Sync & ADC trigger points.
- Fault handling basics.
| Exercise: | HRTIM PWM pair | |
- PWM → ADC sampling.
- Scaling & fixed-point tips.
- Saturation & anti-windup.
- Simple PI step test.
- Update rate budgeting.
| Exercise: | PI step demo | |
- UART 8/9-bit, parity.
- RX ring + idle detect.
- SPI CPOL/CPHA, NSS.
- I²C Fm+ and timeouts.
- Bus-clear recovery.
| Exercise: | Comms trio | |
- Classic vs FD basics.
- Nominal/data bitrates.
- Filters & message RAM.
- Loopback/silent modes.
- Transceiver notes.
| Exercise: | FD loopback | |
- Sleep/Stop/Standby.
- Wake sources (EXTI/RTC).
- LSE vs LSI trade-offs.
- LPTIM tickless scheme.
- GPIO leakage states.
| Exercise: | Stop + wake | |
- Page erase/program.
- EEPROM emulation.
- OB: RDP/WRP/BOR.
- Reset cause logging.
- Watchdogs IWDG/WWDG.
- Clocking proven (MCO).
- I/O safe at boot/sleep.
- ADC chain documented.
- Comms error policy.
- Version/UID/CRC tags.
| Exercise: | Self-audit | |
- CMSIS-DSP quick tips.
- Simple FFT sanity.
- FMAC FIR tuning.
- HRTIM event logging.
- ADC calibration pass.
| Exercise: | Quick pick: choose one mini-demo and record outcome. | |
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To book a training session or for more information, please contact us on info@ac6-training.com.
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This course can be provided either remotely, in our Paris training center or worldwide on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.
Last update of course schedule: 3 October 2024
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