STP1 | SPEAr 1310 implementation |
This course covers the software and hardware implementation of ST Spear 1310 high-end SoC
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Objectives
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- This course provides an overview of the ARM Cortex-A9 core. Our course reference RA2 - Cortex-A9 implementation course details the operation of this core.
- The following courses could be of interest:
- USB Full Speed High Speed and USB On-The-Go, reference IP2 - USB 2.0 course
- Ethernet and switching, reference N1 - Ethernet and switching course
- IEEE1588, reference N2 - IEEE1588 - Precise Time Protocol course
- CAN bus, reference IA1 - CAN bus course
- SD / MMC, reference IS2 - eMMC 5.0 course
- SATA, reference IS3 - Serial ATA III course
- PCI, reference IC1 - PCI 3.0 course
- PCI Express, reference IC4 - PCI Express 3.0 course
- Theoretical course
- PDF course material (in English) supplemented by a printed version for face-to-face courses.
- Online courses are dispensed using the Teams video-conferencing system.
- The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
- At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
- Any embedded systems engineer or technician with the above prerequisites.
- The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
- Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
- At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
- In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
- ARM core based architecture
- On-chip memories
- Clarifying the internal data paths: AXI interconnect, NOC, peripheral buses
- Organization of a board based on SPEAr1310
- Memory mapping
- Presentation of the core, architecture and programming model
- MMU and TLBs
- Level 1 caches
- Cache coherency
- Level 2 cache
- Timers and watchdogs
- Parity protection
- PCM
- Generation of supply switch control signals for power islands
- Generation of shutoff commands for external DDR 1V2 and 1V5/1V8 supply lines
- Monitoring of voltage detector outputs for each power island
- Selecting wake-up sources
- Clock Manager
- Clock sources
- Integrated PLLs
- Clock generators
- System Reset Controller
- System boot mode selection
- Hardware initialization phase
- Startup sequence
- IOMUX module
- General Purpose Input interrupt request capability
- Keyboard controller
- Integrated semaphores
- Temperature sensor
- Cortex-A9MP and PL310 L2 cache IP instantiation options
- Integrated interrupt controller (GIC), detail of interrupt mapping
- Implementing hardware coherency between IO masters and cluster through ACP
- Multi-layer interconnect matrix, crossbars and shared link
- Connectivity matrix
- Introduction to CoreSight, DAP features
- Program Trace Macrocell
- Cross Triggering Interfaces
- Timers
- 4x General-Purpose Timer and High Resolution Timer
- Real Time Clock
- DMA controllers
- DMA multiplexer
- Multi-block transfers achieved through linked lists
- Programmable channel priority
- 16 handshaking interfaces for source and destination peripherals
- Analog-to-Digital converter
- 10-bit resolution
- 8 analog input channels
- DMA hardware handshaking interface
- Serial Management Interface
- SATA II
- Controlling the state of the 3 SATA ports
- Initialization of the controller
- AHCI software host Interface
- Hardware-assisted native command queuing for up to 32 entries
- Integrated DMA channels
- Memory Card Interface (MCIF)
- SD, MMC and SDIO protocols support
- Compact Flash/CF+ Host controller
- Multi-Port DDR Controller
- Introduction to DDR2 and DDR3, write-leveling, ZQ calibration
- Pinout, clocking
- DDR calibration and delay-lines
- Advanced bank look-ahead features for high memory throughput
- Setting DDR-device specific timing parameters
- Reporting errors
- Flexible Static Memory Controller
- External device address mapping
- Interfaces with static memory-mapped devices including NOR flash, SRAM, Cellular SRAM and CosmoRAM
- NAND flash controller with hardware ECC
- External asynchronous wait control
- PCI controller
- 32-bit / 66-MHz operation
- Programmable for acting as host or device
- PCI Express controller
- Muxing SATA and PCIe onto high-speed lanes
- Configuration as Agent or Root Complex
- Interrupt management
- Hot plug support
- Error management
- Synchronous Serial Port
- I2C interfaces
- UART
- USB
- Integrated USB2.0 PHYs
- Explaining what is OTG, SRP and HNP
- High-speed operation
- EHCI support, muxing periodic and non-periodic traffics
- Full speed operation, OHCI
- Gigabit Ethernet Controller
- PHY connection
- Incoming frame filtering mechanisms, hash tables
- VLAN support
- TCP-IP offload
- Audio video (AV) feature, transmitting time-sensitive informations
- IEEE1588 protocol support, timestamp registers
- Media Information Base
- CAN controller
- CAN protocol basics
- message objects
- One Time Programming interfaces
- Security Coprocessor C3
- Multipurpose, instruction driven, programmable DMA-based co-processor
- Sequence to encrypt / decrypt data
- Sequence to generate / check a SHA signature