+ +
- -
Systèmes d'Exploitation
Calendrier  Détails
Programmation
 
Calendrier  Détails
Processeurs ARM
 
Calendrier  Détails
Processeurs PowerPC
 
 
 
 
Calendrier  Détails
Communications
 
Calendrier  Détails
+ +
> >
- -

 
ac6 >> ac6-formation >> Communications >> Network >> IEEE1588 - Precise Time Protocol Télécharger le catalogue Télécharger la page Ecrivez nous Version imprimable

N2 IEEE1588 - Precise Time Protocol

This course describes the PTP protocol and provides implementation examples

formateur
Objectives
  • The course explains the IEEE1588 standard and details some implementation solutions
  • The BMC algorithm is described
  • The course emphasizes the way to implement IEEE1588 on an Ethernet system and highlights the boundary between software and hardware
  • The new features of P1588 (aka IEEE1588v2) are studied
A more detailed course description is available on request at formation@ac6-formation.com
Prerequisites

INTRODUCTION
  • Objectives of the standard
  • The need for synchronization
  • Definitions
PTP CLOCK SYNCHRONIZATION MODEL
  • The PTP messages
  • PTP systems, acyclic graph structure
  • Message filtering
  • Clock properties, stratum, identifier
  • Subdomain properties
PTP PROTOCOL SPECIFICATION
  • Model of a subdomain of PTP clocks
  • State behavior of clocks
  • Protocol engine state machine
  • Clock data sets, initialisation properties
  • Messaging and internal event behavior of clocks
  • Sync-event time-out mechanism
  • Synchronization changes of the local clock
  • Best Master Clock algorithm
  • Clock variance computation
  • Local clock synchronization
  • Physical requirements for PTP implementations
  • Management messages
ETHERNET IMPLEMENTATION OF PTP
  • Ethernet frame type
  • IP header and multicast addresses
  • UDP header, assigned port numbers
  • UDP payload, organization of PTP messages
NXP IMPLEMENTATION OF PTP
  • eTSEC Ethernet MAC
  • Time-stamping
  • Clock correction
  • Trigger inputs
  • Alarms
P1588
  • Mapping to DeviceNet and Ethernet layer-2
  • Prevention of error accumulation in cascaded topologies
  • Rapid network reconfiguration
  • Extensions to enable implementation of redundant systems
  • Optional shorter frame