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ac6 >> ac6-formation >> Processeurs PowerPC >> NXP Power CPUs >> MPC8308 implementation Télécharger le catalogue Télécharger la page Ecrivez nous Version imprimable

FPQ4 MPC8308 implementation

This course covers the PowerQUICC II Pro MPC8308

formateur
Objectives
  • The course explain the architecture of the MPC8308, particularly the operation of the coherency module that interconnects the e300 to memory and high-speed interfaces.
  • Cache coherency protocol is introduced in increasing depth.
  • The e300 core is viewed in detail, especially the MMU .
  • The boot sequence and the clocking are explained.
  • The course focuses on the hardware implementation of the MPC8308.
  • A long introduction to DDR SDRAM operation is done before studying the DDR1/2 SDRAM controller.
  • The course describes the sophisticated QoS mechanisms supported by the eTSEC Ethernet Controllers.
  • Implementation of Precise Time Protocol is also explained.
  • Generation of a Linux image and Root File System by using LTIB can also be included into the training.

  • Products and services offered by ACSYS:
    • ACSYS is able to assist the customer by providing consultancies
    • Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
    • Note that ACSYS has delivered several consultancies on NXP Netcomm SoCs to companies developing avionic equipments.
A more detailed course description is available on request at formation@ac6-formation.com

A lot of programming examples have been developed by ACSYS to explain the boot sequence and the operation of complex peripherals, such as USB and Ethernet.
•  They have been developed with Diab Data compiler and are executed using Lauterbach debugger.
Prerequisites and related courses

INTRODUCTION TO MPC8308
SOC ARCHITECTURE
  • Internal architecture
  • Highlighting data paths inside the MPC8308
  • Software migration from MPC8XX/MPC82XX/MPC85XX families
  • Application examples
THE e300c3 CORE
THE INSTRUCTION PIPELINE
  • Superscalar operation, out-of-order execution, register renaming, serializations, isync instruction
  • Branch processing unit: static prediction vs dynamic prediction
DATA AND INSTRUCTION PATHS
  • Load / store buffers
  • Sync and eieio instructions, determining where eieio is really required
  • Store gathering mechanism
CACHES
  • Cache basics
  • L1 caches
  • Cache coherency mechanism, snooping, related signals
  • The MEI state machine
  • Management of cache enabled pages shared with DMAs
  • Software enforced cache coherency
  • Cache flush routine
SOFTWARE IMPLEMENTATION
  • PowerPC architecture specification, the 3 books UISA, VEA and OEA
  • Addressing modes, load / store instructions
  • Floating point arithmetical instructions
  • The PowerPC EABI
  • Linking an application with Diab Data
THE MMU
  • Introduction to real, block and segmentation / pagination translations
  • Memory attributes and access rights definition
  • TLBs organization
  • Segment-translation
  • Page-translation
  • MMU implementation in real-time sensitive applications
THE EXCEPTION MECHANISM
  • Critical interrupt, automatic nesting
  • Exception management mechanism
  • Requirements to allow exception nesting
THE DEBUG PORT
  • JTAG emulation, restrictions
  • Hardware breakpoints
SOC INFRASTRUCTURE
POWER, RESET AND CLOCKING
  • Power management control
  • Configuration signals sampled at reset
  • Utilization of the I2C boot sequencer
  • Clocking
PLATFORM CONFIGURATION
  • Address translation and mapping
  • Arbiter and bus monitor
  • Timers, software watchdog timer, Real time clock module, Periodic Interval Timer, General Purpose Timers
INTEGRATED PROGRAMMABLE INTERRUPT CONTROLLER
  • Definition of interrupt priorities
  • System critical interrupt
  • Interrupt management, vector register
  • Requirements to support nesting
THE DDR2 MEMORY CONTROLLER
  • DDR-SDRAM operation
  • Jedec specification basics
  • Command truth table
  • Bank activation, read, write and precharge timing diagrams, page mode
  • Initial configuration following Power-on-Reset
  • Address decode
  • Timing parameters programming
ENHANCED LOCAL BUS CONTROLLER
  • Multiplexed or non-multiplexed address and data buses
  • Dynamic bus sizing
  • GPCM, UPMs states machines
  • Nand Flash Controller
  • Booting from NAND flash
ENHANCED SECURE DEVICE HOST CONTROLLER
  • Multi-block transfers
  • Moving data by using the dedicated DMA controller
  • Dividing large data transfers
  • Card insertion and removal detection
PCI EXPRESS INTERFACE
  • Implementation of a unique VC
  • Selectable operation as agent or root complex
  • Address translation
DMA ENGINE
  • Transfer control descriptor format
  • Channel service request
  • Channel-to-channel linking mechanism
  • Scatter/gather DMA processing
CONNECTIVITY
THE USB 2.0 CONTROLLER
  • Dual-role (DR) operation
  • EHCI implementation
  • ULPI interfaces to the transceiver
  • Endpoints configuration
THE ETHERNET CONTROLLERS
  • Frame format with and without VLAN option
  • MAC address recognition
  • Interface with the PHY
  • Buffer descriptors management
  • TCP/IP Offload Engine
  • Quality of service support
  • IEEE1588 frame timestamping
LOW SPEED PERIPHERALS
  • UART
  • I2C
  • SPI controller
Linux Target Image Builder (LTIB)
GENERATING THE LINUX KERNEL IMAGE
  • Introducing the tools required to generate the kernel image
  • What is required on the host before installing LTIB
  • Common package selection screen
  • Common target system configuration screen
  • Building a complete BSP with the default configurations
  • Creating a Root Filesystems image
  • e-configuring the kernel under LTIB
  • Selecting user-space packages
  • Setup the bootloader arguments to use the exported RFS
  • Debugging Uboot and the kernel by using Trace32
  • Command line options
  • Adding a new package
  • Other deployment methods
  • Creating a new package and integrating it into LTIB
    • A lot of labs have been created to explain the usage of LTIB