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ac6 >> ac6-formation >> Processeurs PowerPC >> NXP Power CPUs >> MPC5777M implementation Télécharger le catalogue Télécharger la page Ecrivez nous Version imprimable

FM6 MPC5777M implementation

This course covers the NXP Qorivva MPC5777M microcontroller

formateur
OBJECTIVES
  • This course has the following objectives:
    • Clarifying the architecture of the SoC, especially the split between the computanional shell and the IO complex
    • Providing all informations required to design a board based on MPC5777M, detailing clocking, power management and reset sequence
    • Describing and implementing the safety mechanisms, explaining the purpose of each unit involved in error management
    • Distributing interrupts to the 3 CPUs and relying on eDMA channels to transfer data between IO part and e200z7 RAMs
  • Indicating the capabilities of debug related units, particularly the trace and watchpoint units
    • Detailing the communication modules, such as FlexRAY, CAN and Ethernet controllers.

  • Products and services offered by AC6:
    • AC6 is able to assist the customer by providing consultancies
    • Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
    • A lot of companies developing avionics systems are trusting AC6.
Programming examples have been developed by AC6 to explain the boot sequence and the operation of complex peripherals.
They have been developed with Diab Data compiler and are executed with TRACE32 Lauterbach debugger.

A more detailed course description is available on request at formation@ac6-formation.com
This document is necessary to tailor the course to specific customer needs and to define the exact schedule.
Prerequisites and related courses

ARCHITECTURE OF MPC5777M
  • Block diagram
  • Computational shell
  • Peripheral domain
  • Memory hierarchy
SAFETY MECHANISMS
  • Overview
  • Cyclic Redundancy Check (CRC) Unit
  • Memory Error Management Unit (MEMU)
  • Indirect Memory Access (IMA)
  • Fault Collection and Control Unit (FCCU)
  • Self-Test Control Unit (STCU2)
  • Register Protection (REG_PROT)
CORE COMPLEX OVERVIEW
  • e200z720n3, e200z719, and e200z425n3 cores
  • Microarchitecture summary
EMBEDDED MEMORIES
  • Platform RAM controller
  • Flash memory controller, flash organization
  • Decorated Storage Memory Controller
HARDWARE IMPLEMENTATION
  • Power supplies and reference voltages, power-up sequence
  • Reset Generation Module
  • GPIO multiplexing
  • Clocking
  • External Bus Interface
  • Power Management Controller digital interface
  • Wakeup Unit (WKPU)
SYSTEM MODULES
  • Interconnect parameterizing, introduction to AHB and APB buses
  • Sharing exclusive resources: SEMA42 unit
  • Interrupt controllers, 64 priority levels
  • eDMA controller
  • Timers
SECURITY
  • Overview
  • Password and Device Security Module (PASS)
  • Tamper Detection Module (TDM)
ANALOG MODULES
  • Overview of the integrated ADCs, sample transfer to memory using DMA channels
  • Sigma-Delta Analog-to-Digital Converter
  • Successive Approximation Register Analog-to-Digital Converter
  • Temperature Sensor, calculating device temperature
COMMUNICATION MODULES
  • CAN subsystem
  • Serial Interprocessor Interface (SIPI)
  • LVDS Fast Asynchronous Serial Transmission (LFAST)
  • Fast Ethernet Controller (FEC)
  • FlexRay
  • Deserial Serial Peripheral Interface
  • Inter-Integrated Circuit
  • Peripheral Sensor Interface (PSI5)
  • SENT Receiver (SRX)
  • LINFlexD
CALIBRATION AND DEBUG MODULES
  • Core debug support
  • e200z425n3 Core Debug Support
  • e200z720n3 Core Debug Support
  • Debug and Calibration Interface
  • JTAG Controllers
  • Sequence Processing Unit (SPU)
  • Development Trigger Semaphore (DTS)
  • Nexus Aurora Router (NAR)
  • GTM Development Interface
  • Emulation and Debug Device Introduction