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ac6 >> ac6-formation >> Programmation >> Logique Programmable >> Advanced VHDL for FPGA Télécharger le catalogue Télécharger la page Ecrivez nous Version imprimable

V2 Advanced VHDL for FPGA

Acquire a strong design methodology with the best of VHDL for simulation and synthesis

formateur
Objectives
  • Take the best of VHDL language for logical synthesis and simulation
  • Implementing combinational and sequential logic
  • Developing Finite State Machines
  • Organizing the code developing package and libraries
  • Reusing components
  • Learning how to write efficient test benches for simulation
  • Knowing the different writing style and their impact on the quality of synthesis results
  • Checking Timings
  • Synthesis and Place & Route results parameterizing
Course environment
  • A PC in pairs
  • Xilinx ISE Design Suite v.14.7 IDE / Xilinx Vivado v.2013.4 IDE
  • Nexys-3 (Xilinx Spartan6-based) board / Nexys-4 (Xilinx Artix7-based) board
Prerequisites
  • Knowledge of digital technology
  • Basic knowledge of the VHDL language

First day
Reminders
  • Entity, architecture and process, Library use (IEEE)
  • Elaboration
  • Constants, signals
  • Scalar Types
  • Predefined operators
  • Type conversion, conversion functions
  • Qualified Expressions
  • Aggregates
  • Sequential Statements
    • If, Case, Loop Statements
  • Best practices of efficient coding
Exercise :  Designing a 4-bit adder
Hardware design methodology for logical synthesis
  • Synthesizing combinational and sequential logic
  • Composite Data types and Operations
    • Arrays
    • Unconstrained Array types
    • Array operations and Referencing
    • Records
  • Aliases
  • Predefined and Standard Packages
  • Drivers and resolution functions
  • Multiple Drivers and Tristates
  • Handling 'X' on the inputs
  • Attributes
    • Attributes of Scalar Types and Array Types
    • Attributes of Signals
  • Guard and Blocks
  • Synchronous designs
    • Use of variables in clocked processes
    • Edge detection
    • Synchronizing reset signals
    • Modeling Memories
Exercise :  Designing a BCD-counter/decounter
Second day
Asynchronous design
  • Asynchronous designs and classic tricks
  • Metastability and operational hazards
  • Why avoid asynchronous sequential processes
    • Inputs
    • Timing Constraints
    • Feedbacks: Transparent Latch, Combinational loop
    • Coping with latency and Out-of-Order completion
    • Generating random numbers
  • Synchronization and communication between clock domains
Exercise :  Metastability and clock domains
Configuring, checking and Improving Synthesis results
  • Checking SSO
  • Synthesis, Map and Place & Route results Analysis
    • FPGA utilization
    • Timing Analysis, Critical path
  • Synthesis and Place & Route parameterizing
    • Timing optimization
    • Area optimization
  • Pipeline notion and implementation
  • Useful predefined attributes in logical synthesis
Exercise :  Improving possible frequency for a simple design
The state machines
  • Mealy and Moore machines
    • Graphic representations
    • Implementation
    • VHDL translation
  • Design principles of an FSM with two processes
  • Reset of a state machine
Exercise :  Designing a burstable RAM controller
Third day
Testbenches and simulation
  • Functional and behavioral simulation (with delays)
    • The VITAL Library
  • VHDL instructions specific to simulation
    • “Wait” and its various forms
    • Delay insertion, “after”
    • “Now”
    • “Simulation Loop”
    • Test vector generation
    • Strings, to_string() operator
    • Assertions
    • Reports
    • Timing verification, Measuring Delay
  • Potential incoherencies between logical synthesis and simulation : how to avoid it
  • Integration of « pseudo logic » to facilitate the analysis of simulation results
Exercise :  Designing and testing a logical address decoder
  • Resolved signals
  • External Names, Monitoring internal signals
  • Force and Release Assignments
  • Subprograms
    • Procedures
    • Functions
    • Overloading
    • Visibility of Declarations
  • Access Types
    • Linked Data structures
    • Shared Variable and Protected types
Exercise :  Developing subprograms to simulate
  • File accesses
    • Files declarations
    • Open/Close operations
    • TEXTIO package
    • Writing and reading of ASCII files
    • Allocation of a data flow from a file / Test vector generation
    • Storage of the simulation results in a file
Exercise :  Enhancing the test bench to read the test vectors in a file and to save the results in another
Fourth day
Advanced VHDL features for optimization and code reuse in logical synthesis
  • Hierarchical division
  • Package and Use Clause
    • Package Declarations
    • Package Bodies
    • Use Clauses
    • Context Declarations and Use
  • Libraries
Exercise :  Creating Package and Libraries and working with them
  • Genericity and automatic configuration of re-usable modules
    • Generic Constants, Generic Types, Generic Lists
    • Generic Subprograms, Generic Packages
Exercise :  Enhancing a 4-bit BCD-counter/decounter to create a generic one
  • Components and Configurations
    • Components
    • Configuring components instances
    • Direct instantiation
    • Basic configurations
    • Multiple levels Configuration
Exercise :  Working with configurations
  • Generate statements
    • Generating Iterative Structures
    • Conditionally Generating Structures
    • Configuration of Generate statement
  • Concurrent instructions “for generate “
Exercise :  Designing a n digits BCD-counter/decounter and displaying it on a 7-segment display