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ac6 >> ac6-formation >> Communication >> DDR SDRAM technology >> DDR4 / LPDDR4 Inquire Download as PDF Write us

SDR1 DDR4 / LPDDR4

This course covers both DDR4 and LPDDR4 SDRAM

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OBJECTIVES
  • The course starts with a summary of DDR3/LPDDR3 specification.
  • Then DDR4 functional description is studied.
  • Differences between LPDDR4 and DDR4 are highlighted.
  • ZQ calibration and write levelling sequences are detailed.
  • The analog part is also described, particularly the tests to be performed using an oscilloscope.
  • An example of DDR4 controller provides an example of programming interface.

A more detailed course description is available on request at training@ac6-training.com
  • Knowledge of SDRAM.

  • Theoretical course
    • PDF course material (in English) supplemented by a printed version for face-to-face courses.
    • Online courses are dispensed using the Teams video-conferencing system.
    • The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
  • At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
  • Any embedded systems engineer or technician with the above prerequisites.
  • The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
  • Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
  • At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
    • In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.

Course Outline

  • DDR3 organization
  • Burst chop mode
  • Initialization sequence, new RESET# signal
  • Dynamic ODT
  • ZQ calibration
  • Topologies, fly-by architecture
  • Write leveling
  • Low power modes
  • Power-up, initialization, and power-off
  • Mode Register Read command
  • Mode register definition
  • Timings for Activate, Read, Write, Precharge
  • Precharge & Auto Precharge clarification
  • Refresh command
  • Low power modes, self-refresh, partial array self refresh, power down, deep power down
  • Temperature sensor
  • CA training sequence
  • ZQ calibration, write levelling
  • Bank group vs Bank address
  • Alert output, CRC for write, Command Address parity
  • Reset and initialization procedure
  • Geardown mode
  • BL8 burst order with CRC enabled
  • Input clock frequency change
  • Write levelling
  • DQ training with MPR
  • Temperature controlled refresh modes
  • ZQ calibration
  • Vref training
  • Timings for Activate, Read, Write, Precharge
  • Read preamble training
  • Low power modes
  • Connectivity test mode
  • Pseudo-Open Drain termination
  • Pinout, addressing
  • 2-channel architecture
  • Power-up, initialization and power-off procedure
  • Mode register definition
  • Activation, read and write timing diagrams
  • LPDDR4 Data Mask (DM) and Data Bus Inversion (DBIdc) function
  • Low power modes
  • Vref training
  • Frequency set point update timing
  • Write levelling procedure
  • Read DQ calibration
  • ZQ calibration
  • On-Die Termination
  • Differential Input Cross Point Voltage
  • Slew rate requirements
  • LVSTL(Low Voltage Swing Terminated Logic) IO System
  • Temperature derating for AC timing
  • CA Rx voltage and timing
  • DQ Rx Voltage and Timing
  • Using an oscilloscope to qualify the interface
  • Example of NXP IP
  • Address multiplexing: bank interleaving vs page interleaving
  • PCB design considerations
  • ECC implementation
  • Tuning parameters
  • Initiating write leveling, hardware vs software calibration
  • Driver analog part configuration
  • Memory testing