R2ARM11 implementation
This course covers ARM1136 and ARM1176 CPUs <p>
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Objectives
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- Knowledge of ARM7/9 or having attended the ARM fundamentals course.
- This course does not include chapters on low level programming.
- ACSYS offers a large set of tutorials to become familiar with RVDS, assembly level programming, compiler hints and tips.
- More than 12 correct answers to ARM11 prerequisites questionnaire.
- Theoretical course
- PDF course material (in English) supplemented by a printed version for face-to-face courses.
- Online courses are dispensed using the Teams video-conferencing system.
- The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
- At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
- Any embedded systems engineer or technician with the above prerequisites.
- The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
- Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
- At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
- In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.
Course Outline
- States and modes
- Exception mechanism
- Instruction sets
- Purpose of CP15
- Block diagram
- Highlighting the instruction path and the data path
- Clarifying the usage of the 4 AHB / AXI ports
- Typical architecture of a SoC based on ARM1136/76
- Pipeline stages
- Branch prediction
- Return stack
- Instruction memory barrier, use case
- Objectives
- Clarifying the transitions between NS OS – Secure Monitor – Secure OS
- Consequences on caches and TLBs
- Secure boot, boot sequence
- Distinguishing the Secure vector table from the NS vector table
- Enabling / disabling invasive and non-invasive secure debug
- Memory types
- Inner and outer cache attributes
- Data memory barrier, data synchronization barrier, use cases
- Objectives of the MMU
- Page descriptors
- Highlighting the new features of the V6 architecture regarding the MMU
- Locking entries in TLB
- Abort status, imprecise abort
- Cache basics
- 4-way set associative caches, virtual indexing, page coloring
- Hit under miss capability
- Maintenance operations
- TCM, address decoding
- DMA channels
- DMA state machine, interrupts
- DMA programming, using virtual addresses
- Centralized address decoding
- Address gating logic
- Arbitration, bus parking
- Address pipelining
- Retry response
- Split response
- AMBA 3
- AXI protocol, the 5 communication channels
- Channel handshake mechanism
- Basic transactions, read burst, write burst
- Protection attributes
- Data buses, utilization of byte write strobes
- Unaligned transfers
- Response signalling, requirement of a default slave
- Atomic access, exclusive vs locked transfers
- ARMv6 load / store exclusive instructions
- Ordering model
- Slave parameters
- AXI interconnection architectures
- Reset sequence, power on reset and warm reset timing diagrams
- Power management, run, standby and shutdown modes
- New dormant mode
- Interface to power manager
- Indicating the purpose of internal buffers
- Write allocate policies
- Write merging
- Event monitoring
- Cache maintenance operations
- Low power interface
- Register block
- The 3 interrupt controller models: simple controller, vectored controller and controller using the VIC port
- Benefit of the VIC port interface
- New feature regarding exceptions: low latency mode
- Performance monitor
- Instruction breakpoints and data watchpoints
- Vector catch hardware
- Thread aware debug
- Halt mode vs monitor mode
- Debug communication channel
- Coresight ETM11
- AMBA Trace Bus, trace port and Embedded Trace Buffer
- Instruction tracing
- Data tracing
- Programming ETM11CS
More
To book a training session or for more information, please contact us on info@ac6-training.com.
Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.
You can also fill and send us the registration form
This course can be provided either remotely, in our Paris training center or worldwide on your premises.
Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.
Last update of course schedule: 23 February 2026
Booking one of our trainings is subject to our General Terms of Sales
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