| Formation Freescale ColdFire - MCF5225X implementation + MQX |
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Vous êtes ici: ac6 > ac6-formation > Freescale ColdFire > MCF5225X implementation + MQX |
| FF5 | MCF5225X implementation + MQX |
| OBJECTIVES | |||
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Courses detail the hardware implementation of the MCF5225x MCU. | ||
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Courses focuse on low level programming of the ColdFire V2 core. | ||
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The training helps become familiar with CodeWarrior IDE. | ||
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Practical exemples of internal software drivers are provided. |
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More detailed course description available on request at info@ac6-training.com |
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| New: *** Write your First Freescale MQX™ RTOS application *** | |||
| Prerequisites | |||
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Experience of a 32 bit processor or DSP is mandatory. |
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| Related courses | |||
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Ethernet and switching, reference N1 |
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USB 2.0, reference IP2 |
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CAN bus, reference IA1 | ||
| Plan |
| INTRODUCTION TO MCF52259 | |||
| Overview | |||
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Coldfire roadmap | ||
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MCF52259 umbrella device | ||
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5225X block diagram | ||
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Pinout | ||
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Memory mapped I/O organization | ||
| CORE ARCHITECTURE | |||
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V2 pipeline | ||
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Addressing modes | ||
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Branch, data transfer, arithmetic, logic, shift & rotate, bit instructions | ||
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Mac instructions | ||
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C to assembly interface | ||
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Section definition, parameterizing the linker command file | ||
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Exception management | ||
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Internal SRAM | ||
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5225X cache operation | ||
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Power management | ||
| DEBUG FACILITIES | |||
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Intrusive vs non-intrusive debug | ||
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BDM port | ||
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Hardware breakpoints | ||
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Trace port | ||
| PLATFORM | |||
| RESET | |||
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Reset sources | ||
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Clocking | ||
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Reset control flow | ||
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Chip Configuration Module [CCM] | ||
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Requirements of the boot routine | ||
| SYSTEM PERIPHERALS | |||
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SCM | ||
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The interrupt controller | ||
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The Edge Port Module | ||
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Watchdog timer module | ||
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Programmable Interrupt Timer Modules | ||
| THE DMA CONTROLLER | |||
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Channel prioritization | ||
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Bandwidth control | ||
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Transfer termination | ||
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Utilization of DMA timers | ||
| HARDWARE IMPLEMENTATION | |||
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Dynamic bus sizing | ||
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Address decoding | ||
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Data transfer sequence | ||
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Burst cycles | ||
| MEMORY | |||
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The Flash memory controller | ||
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The SRAM | ||
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The Mini-FlexBus | ||
| INTEGRATED I/Os | |||
| COMMUNICATION CONTROLLERS | |||
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The UART Module | ||
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The QSPI | ||
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The I2C controller | ||
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The FlexCAN controller | ||
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The USB OTG controller | ||
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The Fast Ethernet Controller | ||
| Exercice : | With Freescale MQX™ software solutions | ||
| CRYPTOGRAPHY | |||
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Cryptographic Acceleration Unit (CAU) | ||
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Random Number Generator (RNG) | ||
| Durée | Prix | Calendrier |
| 4 jours | 1950 € |
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