FF5	MCF5225X implementation + MQX

This course covers MCF5225X ColdFire MCUs, for instance the MCF52259

OBJECTIVES Courses detail the hardware implementation of the MCF5225x MCU. Courses focuse on low level programming of the ColdFire V2 core. The training helps become familiar with CodeWarrior IDE. Practical exemples of internal software drivers are provided. More detailed course description available on request at info@ac6-training.com New: *** Write your First Freescale MQX™ RTOS application ***

Prerequisites Experience of a 32 bit processor or DSP is mandatory. Related courses Ethernet and switching, reference N1 USB 2.0, reference IP2 CAN bus, reference IA1

Plan

INTRODUCTION TO MCF52259 Overview Coldfire roadmap MCF52259 umbrella device 5225X block diagram Pinout Memory mapped I/O organization CORE ARCHITECTURE V2 pipeline Addressing modes Branch, data transfer, arithmetic, logic, shift & rotate, bit instructions Mac instructions C to assembly interface Section definition, parameterizing the linker command file Exception management Internal SRAM 5225X cache operation Power management DEBUG FACILITIES Intrusive vs non-intrusive debug BDM port Hardware breakpoints Trace port PLATFORM RESET Reset sources Clocking Reset control flow Chip Configuration Module [CCM] Requirements of the boot routine SYSTEM PERIPHERALS SCM The interrupt controller The Edge Port Module Watchdog timer module Programmable Interrupt Timer Modules

THE DMA CONTROLLER Channel prioritization Bandwidth control Transfer termination Utilization of DMA timers HARDWARE IMPLEMENTATION Dynamic bus sizing Address decoding Data transfer sequence Burst cycles MEMORY The Flash memory controller The SRAM The Mini-FlexBus INTEGRATED I/Os COMMUNICATION CONTROLLERS The UART Module The QSPI The I2C controller The FlexCAN controller The USB OTG controller The Fast Ethernet Controller Exercice : With Freescale MQX™ software solutions CRYPTOGRAPHY Cryptographic Acceleration Unit (CAU) Random Number Generator (RNG)

 

Durée	Prix	Calendrier
4 jours	1950 €