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FF5 MCF5225X implementation + MQX

This course covers MCF5225X ColdFire MCUs, for instance the MCF52259


formateur
OBJECTIVES
bullet_jaune_1 Courses detail the hardware implementation of the MCF5225x MCU.
bullet_jaune_1 Courses focuse on low level programming of the ColdFire V2 core.
bullet_jaune_1 The training helps become familiar with CodeWarrior IDE.
bullet_jaune_1 Practical exemples of internal software drivers are provided.
bullet_jaune_1 More detailed course description available on request at info@ac6-training.com
New: *** Write your First Freescale MQX™ RTOS application ***
Prerequisites
bullet_jaune_2 Experience of a 32 bit processor or DSP is mandatory.
Related courses
bullet_jaune_2 Ethernet and switching, reference N1
bullet_jaune_2 USB 2.0, reference IP2
bullet_jaune_2 CAN bus, reference IA1


Outline
INTRODUCTION TO MCF52259
Overview
bullet_jaune_2 Coldfire roadmap
bullet_jaune_2 MCF52259 umbrella device
bullet_jaune_2 5225X block diagram
bullet_jaune_2 Pinout
bullet_jaune_2 Memory mapped I/O organization
CORE ARCHITECTURE
bullet_jaune_2 V2 pipeline
bullet_jaune_2 Addressing modes
bullet_jaune_2 Branch, data transfer, arithmetic, logic, shift & rotate, bit instructions
bullet_jaune_2 Mac instructions
bullet_jaune_2 C to assembly interface
bullet_jaune_2 Section definition, parameterizing the linker command file
bullet_jaune_2 Exception management
bullet_jaune_2 Internal SRAM
bullet_jaune_2 5225X cache operation
bullet_jaune_2 Power management
DEBUG FACILITIES
bullet_jaune_2 Intrusive vs non-intrusive debug
bullet_jaune_2 BDM port
bullet_jaune_2 Hardware breakpoints
bullet_jaune_2 Trace port
PLATFORM
RESET
bullet_jaune_2 Reset sources
bullet_jaune_2 Clocking
bullet_jaune_2 Reset control flow
bullet_jaune_2 Chip Configuration Module [CCM]
bullet_jaune_2 Requirements of the boot routine
SYSTEM PERIPHERALS
bullet_jaune_2 SCM
bullet_jaune_2 The interrupt controller
bullet_jaune_2 The Edge Port Module
bullet_jaune_2 Watchdog timer module
bullet_jaune_2 Programmable Interrupt Timer Modules
THE DMA CONTROLLER
bullet_jaune_2 Channel prioritization
bullet_jaune_2 Bandwidth control
bullet_jaune_2 Transfer termination
bullet_jaune_2 Utilization of DMA timers
HARDWARE IMPLEMENTATION
bullet_jaune_2 Dynamic bus sizing
bullet_jaune_2 Address decoding
bullet_jaune_2 Data transfer sequence
bullet_jaune_2 Burst cycles
MEMORY
bullet_jaune_2 The Flash memory controller
bullet_jaune_2 The SRAM
bullet_jaune_2 The Mini-FlexBus
INTEGRATED I/Os
COMMUNICATION CONTROLLERS
bullet_jaune_2 The UART Module
bullet_jaune_2 The QSPI
bullet_jaune_2 The I2C controller
bullet_jaune_2 The FlexCAN controller
bullet_jaune_2 The USB OTG controller
bullet_jaune_2 The Fast Ethernet Controller
Exercice : With Freescale MQX™ software solutions
CRYPTOGRAPHY
bullet_jaune_2 Cryptographic Acceleration Unit (CAU)
bullet_jaune_2 Random Number Generator (RNG)