| Formation Freescale ColdFire - MCF5x07 implementation |
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Vous êtes ici: ac6 > ac6-formation > Freescale ColdFire > MCF5x07 implementation |
| FF1 | MCF5x07 implementation |
| Objectives | |||
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The course describes the ColdFire assembly language and highlights differences from 68K instructions. |
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An example of SDRAM controller initialization is provided. |
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Interfacing with external devices is explained. |
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The interrupt controller is viewed in detail. |
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Interrupt driven DMA transfers are studied. |
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A programming example has been developped for each internal peripheral (serial; I2C, timer). | ||
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This course has been delivered several times to companies developing industrial and avionics systems. | ||
| A lot of programming examples have been developed by ACSYS to explain the boot sequence and the operation of peripherals. •They have been developed with Diab Data compiler and are executed under Lauterbach debugger. |
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| A more detailed course description is available on request at info@ac6-training.com | |||
| Prerequisites | |||
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Experience of a 32 bit processor or DSP is mandatory. | ||
| Plan |
| MCF5307 ARCHITECTURE | |||
| Overview | |||
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Coldfire roadmap | ||
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Differences between ColdFires and 68K processors | ||
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5307 block diagram | ||
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Pinout | ||
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Memory mapped I/O organization | ||
| V3 CORE | |||
| CORE ARCHITECTURE | |||
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5307 pipeline | ||
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Programming model | ||
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Addressing modes | ||
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Instruction set | ||
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Stack management, subroutine call and return | ||
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C to assembly interface | ||
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Exception management | ||
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Internal SRAM | ||
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5307 cache operation | ||
| CORE DEBUG | |||
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Intrusive vs non-intrusive debug | ||
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BDM port | ||
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Hardware breakpoints | ||
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Trace port | ||
| PLATFORM | |||
| HARDWARE IMPLEMENTATION | |||
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Dynamic bus sizing | ||
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Address decoding | ||
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Arbitration | ||
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Burst cycles | ||
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Bus error management | ||
| THE SIM MODULE | |||
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The interrupt controller | ||
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The software watchdog | ||
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Reset, self-configuration | ||
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Clock synthesis | ||
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General Purpose I/O pins | ||
| THE MEMORY CONTROLLER AND THE DRAM/SDRAM CONTROLLER | |||
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SRAM connection, chip-select programming | ||
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DRAM / SDRAM basics | ||
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The 5x07 (S)DRAM controller : address decoding, refresh rate definition, address multiplexing selection | ||
| INTEGRATED I/Os | |||
| THE SERIAL PORTS | |||
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Asynchronous ports | ||
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Transmit and receive sequences | ||
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Synchronous port : I2C basics | ||
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Transmit and receive sequences | ||
| THE DMA CONTROLLER | |||
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Single address vs dual address transfers | ||
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Hardware interface, hardware initiated transfers | ||
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Programming model | ||
| THE TIMERS | |||
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Capture mode | ||
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Period selection | ||
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Interrupt control | ||
| MCF5407 ENHANCEMENTS | |||
| MCF5407 | |||
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V4 core enhancements | ||
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Instruction set additions | ||
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Enhanced memories | ||
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On-chip DMA and serial ports modifications | ||
| Durée | Prix | Calendrier |
| 4 jours | 1950 € |
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