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| Architecture of MCIMX51 |
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Clarifying the internal data paths : AXI interconnect, AHB bus, peripheral buses |
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Highlighting the purpose of the 2 central interconnect units : MAX and M4IF |
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Organization of a board based on MCIMX51 |
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Mapping |
| The ARM Cortex/A8 Core - Overview |
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Operating modes : user, system, super, IRQ, FIQ, undef and abort |
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ARM vs Thumb-2 instruction sets, interworking |
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Access to memory-mapped locations, addressing modes |
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Stack management |
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Branch instructions, implementation of C call and return statements |
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Level1 cache operation |
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Level2 cache operation |
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Memory management unit, TLB |
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C-to-Assembly interface |
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Exception mechanism, handler table |
| Reset and Clocking |
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Clock distribution |
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DVFS support |
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Power Gating Controller |
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Low power modes, wake-up detector |
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Global reset vs warm reset |
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System boot mode selection |
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eFUSE configuration |
| System Control |
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GPIO module |
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General Purpose Input interrupt request capability |
| The Cortex/A8 Platform |
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MAX parameterizing |
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ARM Vector Interrupt Controller |
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Integrated timers EPIT, GPT, WDT |
| Debug Architecture |
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Introduction to CoreSight, DAP features |
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System Secure Controller SJC |
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Embedded Trace Macrocell |
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Cross Triggering Interfaces |
| Smart DMA Controller |
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Mapping DMA requests to channels |
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Channel priority definition |
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Scheduler |
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Instruction description |
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PCU states |
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Context switching |
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Reference clocks and low power modes |
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Debug support |
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Profiling unit |
| Accessing External Memories |
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Description of the Master Arbitration and Buffering [MAB] unit |
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Description of the M4IF arbitration [M3A] unit |
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Introduction to DDR2/LPDDR SDRAM |
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Enhanced DDR2 SDRAM controller |
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NAND flash controller, boot from flash |
| System Security |
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Security Controller |
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Protecting information and data from unauthorized access |
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A dedicated AES cryptographic engine |
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High Assurance Boot |
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SAHARA4 security coprocessor |
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Random number generator |
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Encryption / decryption sequences |
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Restricted access to potentially sensitive information |
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ARM TrustZone support |
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Run-Time Integrity Checker |
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SHA-1 and SHA-256 message authentication |
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Segmented data gathering |
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One-time hash mode vs continuous hash mode |
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IC Identification Module |
| Standard Parrallel Interfaces |
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ATA controller |
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Pinout |
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PIO mode |
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Ultra DMA mode |
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Enhanced SDHC |
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Interface to SD, MMC, SDIO and CE-ATA cards |
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Transfer protocol, single block, multiple block read and write |
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Internal and external DMA capabilities |
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Error management |
