i.MX31 implementation + LTIB Training | Ac6 Formation

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FA2i.MX31 implementation + LTIB
This course describes the i.MX31 multimedia processor and Linux Target Image Builder tool
Objectives
  • The course details the hardware implementation of the i.MX31 microcontroller.
  • The boot sequence and the clocking are explained.
  • The course explains all parameters that affect the performance of the system in order to easily perform the final tuning.
  • A description of all internal peripherals is provided.
  • An overview of the ARM1136 core helps to understand issues caused by cache and MMU.
  • The course ends with practical labs explaining how to generate a Linux image as well as a Root File System, by using a tool called LTIB [Linux Target Image Builder].

  • Products and services offered by ACSYS:
    • ACSYS has developed FFTs (floating-point and fixed-point) optimized for ARM cores, based on SIMD instructions supported by the ARM1136.
    • Contact formation@ac6-formation.com to obtain informations about the performance of these FFTs.
    • ACSYS is able to assist the customer by providing consultancies. Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
    • ACSYS has also an expertise in programming the SDMA, a simple OS-agnostic driver has been developed to explain how to manage scripts.

This course has been delivered several times to companies developing multimedia equipments.
Program examples have been developed by ACSYS to explain the boot sequence and the operation of complex peripherals.
•  They are compiled by the GNU compiler and are executed under Lauterbach debugger.
•  A host desktop running Linux is used to generate Linux image and Root File System during labs on LTIB.
A more detailed course description is available on request at formation@ac6-formation.com

Related courses
Course IP2 - USB 2.0Course IS2 - eMMC 5.0Course R2 - ARM11 implementationCourse D1L - Linux embarqué NXP avec LTIB
  • Knowledge of ARM1136JF-S is recommended, see our course reference R2.
  • Knowledge of USB is recommended, see our course reference IP2 - USB 2.0 course
  • ACSYS also offer a large set of courses on Linux.
  • Theoretical course
    • PDF course material (in English) supplemented by a printed version for face-to-face courses.
    • Online courses are dispensed using the Teams video-conferencing system.
    • The trainer answers trainees' questions during the training and provide technical and pedagogical assistance.
  • At the start of each session the trainer will interact with the trainees to ensure the course fits their expectations and correct if needed
  • Any embedded systems engineer or technician with the above prerequisites.
  • The prerequisites indicated above are assessed before the training by the technical supervision of the traineein his company, or by the trainee himself in the exceptional case of an individual trainee.
  • Trainee progress is assessed by quizzes offered at the end of various sections to verify that the trainees have assimilated the points presented
  • At the end of the training, each trainee receives a certificate attesting that they have successfully completed the course.
    • In the event of a problem, discovered during the course, due to a lack of prerequisites by the trainee a different or additional training is offered to them, generally to reinforce their prerequisites,in agreement with their company manager if applicable.

Course Outline

  • Clarifying the internal data paths : AHB bus, peripheral buses
  • Highlighting the purpose of the 2 central interconnect units : MAX and M3IF
  • Organization of a board based on i.MX31
  • Presentation of the core, architecture and programming model
  • Operating modes : user, system, super, IRQ, FIQ, undef and abort
  • ARM vs Thumb instruction sets, interworking
  • Branch instructions, implementation of C call and return statements
  • Level1 cache operation
  • Memory management unit
  • C-to-Assembly interface
  • Exception mechanism, handler table
  • Debug facilities
  • MAX parameterizing
  • ARM Vector Interrupt Controller
  • Level 2 cache operation
  • Clock distribution
  • PLL output frequency calculation
  • Power-up sequence
  • Low power modes, clock gating
  • Global reset vs warm reset
  • System boot mode selection
  • GPIO module
  • General Purpose Input interrupt request capability
  • Signal description
  • Description of the Master Arbitration and Buffering [MAB] unit
  • Description of the M3IF arbitration [M3A]
  • Introduction to DDR SDRAM
  • Enhanced DDR SDRAM controller
  • NAND flash controller, boot from flash
  • ATA controller
  • MSHC
  • SDHC
  • Scheduler
  • CRC calculation unit
  • SDMA initialisation
  • Instruction description
  • Video acquisition
  • MPEG4 encoder
  • Image Processing Unit
  • Graphics accelerator
  • SSI interfaces
  • Digital audio multiplexor
  • 1-wire interface
  • Configurable SPI
  • I2C interfaces
  • UART
  • USB
  • Introducing the tools required to generate the kernel image
  • What is required on the host before installing LTIB
  • Common package selection screen
  • Common target system configuration screen
  • Building a complete BSP with the default configurations
  • Creating a Root Filesystems image
  • Re-configuring the kernel under LTIB
  • Selecting user-space packages
  • Setup the bootloader arguments to use the exported RFS
  • Debugging Uboot and the kernel by using Trace32
  • Command line options
  • Adding a new package
  • Other deployment methods
  • Creating a new package and integrating it into LTIB
Duration
4 days
Inquiry

This course can be scheduled upon request. Click the 'Inquire' button to contact us.

More

To book a training session or for more information, please contact us on info@ac6-training.com.

Registrations are accepted till one week before the start date for scheduled classes. For late registrations, please consult us.

You can also fill and send us the registration form

This course can be provided either remotely, in our Paris training center or worldwide on your premises.

Scheduled classes are confirmed as soon as there is two confirmed bookings. Bookings are accepted until 1 week before the course start.

Last update of course schedule: 25 April 2026

Booking one of our trainings is subject to our General Terms of Sales

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