View the site in Français View the site in English (USA) Site displayed in English (GB)
You are here: ac6 > ac6-formation > NXP processors > LPC17xx Implementation
Download Catalog
Download Catalog
Download as PDF
Download as PDF
Write us
Write us
Printable version
Printable version
 

NP2 LPC17xx Implementation

This course covers NXP Cortex-M3-based MCU family.


formateur
Objectives
bullet_jaune_1 The course describes Cortex-M3 architecture from ARM.
bullet_jaune_1 Then it clarifies the LPC17xx implementation: LPC1768, LPC1766, LPC1765, LPC1764, LPC1758, LPC1756, LPC1754, LPC1752, LPC1751
bullet_jaune_1 Both hardware and low level software are detailed.
bullet_jaune_1 Practical labs on integrated peripherals are done during the training.
Material
bullet_jaune_2 One PC and one evaluation board for two students.
bullet_jaune_2 HW: KEIL ULINK2 debug interface and MCB1700 evaluation board
bullet_jaune_2 SW: KEIL µVision Integrated Development Environment
Prerequisites
bullet_jaune_2 Knowledge of processors is essential
bullet_jaune_2 Understanding assembler and C language is recommended.
bullet_jaune_2 A basic awareness of ARM architecture would be useful.
Related courses
bullet_jaune_2 Regarding in depth knowledge of complex peripherals, ACSYS offers the following trainings:
bullet_jaune_2 Ethernet and Switching (ref. N1), USB 2 (ref. I6), CAN bus (ref. I9).
bullet_jaune_2 Note that ACSYS can tailor the course to your needs by mixing several courses.

Outline
Introduction to ARM Cortex-M3 Architecture and NXP LPC17xx Implementation
bullet_jaune_2 Architecture versus implementation
bullet_jaune_2 ARM Cortex-M3 architecture (V7-M)
bullet_jaune_2 LPC17xx implementation
bullet_jaune_2 AHB and APB internal buses
bullet_jaune_2 Memory mapping
bullet_jaune_2 ARM instruction set evolution
bullet_jaune_2 ARM, Thumb and Thumb2 instruction set
bullet_jaune_2 Programming model
Thumb2 instruction set
bullet_jaune_2 Introduction
bullet_jaune_2 General points on syntax
bullet_jaune_2 Data processing instructions
bullet_jaune_2 Branch and control flow instructions
bullet_jaune_2 Memory access instructions
bullet_jaune_2 Exception generating instructions
bullet_jaune_2 If…then conditional blocks
bullet_jaune_2 Stack in operation
bullet_jaune_2 Exclusive load and store instructions
bullet_jaune_2 Accessing special registers
bullet_jaune_2 Coprocessor instructions
bullet_jaune_2 Memory barriers and synchronisation
Interrupts
bullet_jaune_2 Basic interrupt operation, micro-coded interrupt mechanism
bullet_jaune_2 Interrupt entry / exit, timing diagrams
bullet_jaune_2 Interrupt stack
bullet_jaune_2 Tail chaining
bullet_jaune_2 Interrupt response, pre-emption
bullet_jaune_2 NVIC registers
bullet_jaune_2 Interrupt prioritization
bullet_jaune_2 Interrupt implementation configurability, impact on core size
bullet_jaune_2 Interrupt handlers
Exceptions
bullet_jaune_2 Exception behavior, exception return
bullet_jaune_2 Non-maskable exceptions
bullet_jaune_2 Privilege, modes and stacks
bullet_jaune_2 Fault escalation
bullet_jaune_2 Priority boosting
bullet_jaune_2 Vector table
Cortex-M3 Core
bullet_jaune_2 Block diagram
bullet_jaune_2 Programmer’s model, special purpose registers
bullet_jaune_2 State, privilege and stacks
bullet_jaune_2 Data path and pipeline, pipeline flushing, speculative branch target pre-fetch, folding
bullet_jaune_2 Write buffer
bullet_jaune_2 Bit-banding
bullet_jaune_2 Alignment and endianness
bullet_jaune_2 System timer
bullet_jaune_2 System control block
bullet_jaune_2 Debug
LPC17xx hardware implementation
bullet_jaune_2 Pin out
bullet_jaune_2 Power supply and regulator, power domains
bullet_jaune_2 Clocking
bullet_jaune_2 Reset
bullet_jaune_2 Brownout Detector
LPC17xx Peripherals
bullet_jaune_2 General Purpose Input Output
bullet_jaune_2 Timer Unit
bullet_jaune_2 UART Controller
bullet_jaune_2 DMA Controller
bullet_jaune_2 I2C
bullet_jaune_2 SPI/SSP
bullet_jaune_2 USB
bullet_jaune_2 Ethernet
KEIL IDE overview
bullet_jaune_2 Introduction to µvision
bullet_jaune_2 Project creation
bullet_jaune_2 Adding files to the project
bullet_jaune_2 Parameterize the IDE, indicating the location of RAM and ROM
bullet_jaune_2 Initialization file
bullet_jaune_2 Generating the executable file
bullet_jaune_2 Launching the simulator
bullet_jaune_2 Using the basic commands of the simulator
bullet_jaune_2 Downloading the application to the target board, flashing
bullet_jaune_2 Running the program
bullet_jaune_2 Stopping the debug session
C compiler hints and tips for Cortex-M3
bullet_jaune_2 ARM compiler optimisations, tail-call optimization, in lining of functions
bullet_jaune_2 Mixing C/C++ and assembly
bullet_jaune_2 Coding with ARM compiler
bullet_jaune_2 Measuring stack usage
bullet_jaune_2 Unaligned accesses
bullet_jaune_2 Local and global data issues, alignment of structures
bullet_jaune_2 Further optimisations, linker feedback
Embedded software and development with Cortex-M3
bullet_jaune_2 Embedded development process
bullet_jaune_2 Application start up
bullet_jaune_2 Placing code, data, stack and heap in the memory map, scatter loading
bullet_jaune_2 Tailoring the C library to your target
bullet_jaune_2 Reset and initialisation
bullet_jaune_2 Placing a minimal vector table
bullet_jaune_2 Further memory map considerations, 8-byte stack alignment in handlers
bullet_jaune_2 Building and debugging your image
bullet_jaune_2 Long branch veneers