NP2	LPC17xx Implementation

This course covers NXP Cortex-M3-based MCU family.

Objectives The course describes Cortex-M3 architecture from ARM. Then it clarifies the LPC17xx implementation: LPC1768, LPC1766, LPC1765, LPC1764, LPC1758, LPC1756, LPC1754, LPC1752, LPC1751 Both hardware and low level software are detailed. Practical labs on integrated peripherals are done during the training.

Material One PC and one evaluation board for two students. HW: KEIL ULINK2 debug interface and MCB1700 evaluation board SW: KEIL µVision Integrated Development Environment Prerequisites Knowledge of processors is essential Understanding assembler and C language is recommended. A basic awareness of ARM architecture would be useful.

Related courses Regarding in depth knowledge of complex peripherals, ACSYS offers the following trainings: Ethernet and Switching (ref. N1), USB 2 (ref. I6), CAN bus (ref. I9). Note that ACSYS can tailor the course to your needs by mixing several courses.

Outline

Introduction to ARM Cortex-M3 Architecture and NXP LPC17xx Implementation Architecture versus implementation ARM Cortex-M3 architecture (V7-M) LPC17xx implementation AHB and APB internal buses Memory mapping ARM instruction set evolution ARM, Thumb and Thumb2 instruction set Programming model Thumb2 instruction set Introduction General points on syntax Data processing instructions Branch and control flow instructions Memory access instructions Exception generating instructions If…then conditional blocks Stack in operation Exclusive load and store instructions Accessing special registers Coprocessor instructions Memory barriers and synchronisation Interrupts Basic interrupt operation, micro-coded interrupt mechanism Interrupt entry / exit, timing diagrams Interrupt stack Tail chaining Interrupt response, pre-emption NVIC registers Interrupt prioritization Interrupt implementation configurability, impact on core size Interrupt handlers Exceptions Exception behavior, exception return Non-maskable exceptions Privilege, modes and stacks Fault escalation Priority boosting Vector table Cortex-M3 Core Block diagram Programmer’s model, special purpose registers State, privilege and stacks Data path and pipeline, pipeline flushing, speculative branch target pre-fetch, folding Write buffer Bit-banding Alignment and endianness System timer System control block Debug

LPC17xx hardware implementation Pin out Power supply and regulator, power domains Clocking Reset Brownout Detector LPC17xx Peripherals General Purpose Input Output Timer Unit UART Controller DMA Controller I2C SPI/SSP USB Ethernet KEIL IDE overview Introduction to µvision Project creation Adding files to the project Parameterize the IDE, indicating the location of RAM and ROM Initialization file Generating the executable file Launching the simulator Using the basic commands of the simulator Downloading the application to the target board, flashing Running the program Stopping the debug session C compiler hints and tips for Cortex-M3 ARM compiler optimisations, tail-call optimization, in lining of functions Mixing C/C++ and assembly Coding with ARM compiler Measuring stack usage Unaligned accesses Local and global data issues, alignment of structures Further optimisations, linker feedback Embedded software and development with Cortex-M3 Embedded development process Application start up Placing code, data, stack and heap in the memory map, scatter loading Tailoring the C library to your target Reset and initialisation Placing a minimal vector table Further memory map considerations, 8-byte stack alignment in handlers Building and debugging your image Long branch veneers

 

Duration	Cost	Calendar
4 days	0 €