View the site in Français Site displayed in English (USA) View the site in English (GB)
You are here: ac6 > ac6-formation > NXP processors > LPC21XX/LPC22XX microcontroller implementation

NP1 LPC21XX/LPC22XX microcontroller implementation

This course covers NXP ARM-based MCU family

Objectives
bullet_jaune_1 The course details the hardware implementation of the LPC2294 microcontrollers.
bullet_jaune_1 The boot sequence and the clocking are explained.
bullet_jaune_1 The training helps to become familiar with the development environment chosen by the customer.
bullet_jaune_1 Practical labs on integrated peripherals are based on I/O functions provided by NXP.
bullet_jaune_1 The course focuses on the low level programming of the ARM7TDMI core.
bullet_jaune_1 The course provides examples of internal peripheral software drivers.

bullet_jaune_1 Note that ACSYS does not sell emulation probes and IDEs. Consequently this course has not been designed to convince attendees to buy a particular IDE. The unique objective consists in providing sufficient knowledge to attendees so that they can successfully design a system based on LPC21XX/LPC22XX.

bullet_jaune_1 This course has been delivered several times to companies developing embedded systems, such as voltage counters.
A lot of programming examples have been developed by ACSYS to explain the boot sequence, the vector table and the operation of embedded peripherals.

  •They have been developed with 2 different IDEs : Keil and IAR.

  •Consequently for on site course, it is up to the customer to select the IDE under which labs will be run.
A more detailed course description is available on request at info@ac6-formation.com
Prerequisites and related courses
bullet_jaune_2 This course provides an overview of the ARM7TDMI core. Our course reference R1 details the operation of this core.
bullet_jaune_2 The following course could be of interest:
bullet_jaune_3 CAN bus, reference IA1

Outline
INTRODUCTION TO LPC2210 AND LPC2294
Overview
bullet_jaune_2 ARM core based architecture
bullet_jaune_2 ARM7 local bus
bullet_jaune_2 AMBA AHB/APB internal buses
bullet_jaune_2 The main three blocks : platform, core and input / output peripherals
bullet_jaune_2 APB Bridges
bullet_jaune_2 Memory mapping, internal flash (2294) and SRAM
THE PROCESSOR CORE
ARCHITECTURE OF THE ARM7TDMI CORE
bullet_jaune_2 Presentation of the core, architecture and programming model
bullet_jaune_2 Operating modes : user, system, super, IRQ, FIQ, undef and abort
bullet_jaune_2 Pipeline, calculation of the CPI
bullet_jaune_2 Effects of branches and exceptions on the performance
bullet_jaune_2 ALU data path
SOFTWARE IMPLEMENTATION, V4T SPECIFICATION
bullet_jaune_2 Parameterizing the linker to define sections
bullet_jaune_2 Branch instructions, implementation of C call and return statements, long branch veneers
bullet_jaune_2 ARM vs Thumb instruction sets, interworking
bullet_jaune_2 ARM instruction set
bullet_jaune_2 Inline barrel shifter
bullet_jaune_2 Access to memory-mapped locations, addressing modes
bullet_jaune_2 Arithmetical and logic instructions
bullet_jaune_2 Thumb instruction set, highlighting restrictions with regard to ARM instruction set
bullet_jaune_2 Compiler hints and tips, optimisations supported by RVCT
bullet_jaune_2 Stack management
bullet_jaune_2 Benefits of condition set capability in ARM state
bullet_jaune_2 C-to-Assembly interface, ATPCS specification
EXCEPTION MECHANISM
bullet_jaune_2 Reset
bullet_jaune_2 FIQ vs IRQ
bullet_jaune_2 Exception return instructions
bullet_jaune_2 Latency estimation, impact of load and store multiple instructions
bullet_jaune_2 Organization of the handler table, priority decoder, pre-emption and nesting
bullet_jaune_2 ISR header and footer routines
bullet_jaune_2 Development of a generic exception handler
INTEGRATED DEBUG FACILITIES
bullet_jaune_2 JTAG interface
bullet_jaune_2 Debug facilities, hardware breakpoint
bullet_jaune_2 Executing code from RAM to take benefit of software breakpoints
PLATFORM
THE VECTORED INTERRUPT CONTROLLER
bullet_jaune_2 Assigning a priority to each interrupt source
bullet_jaune_2 Steering external interrupts and local interrupts to either the core FIQ or IRQ
bullet_jaune_2 Developing a generic interrupt handler performing nesting according to peripheral priorities defined by the user
bullet_jaune_2 Integrated timers
bullet_jaune_2 Using timers to understand the operation of the VIC
SYSTEM CONTROL
bullet_jaune_2 Pin connect block
bullet_jaune_2 Clocking
bullet_jaune_2 Reset and wake-up timer
bullet_jaune_2 Low power modes
bullet_jaune_2 Watchdog timer
bullet_jaune_2 Real-Time clock
ON-CHIP FLASH MEMORY (2294)
bullet_jaune_2 Organization
bullet_jaune_2 Erase sequence
bullet_jaune_2 Program sequence
bullet_jaune_2 In system programming via serial port
bullet_jaune_2 On-chip bootloader
EXTERNAL MEMORY CONTROLLER
bullet_jaune_2 Address decoding
bullet_jaune_2 Chip-select registers
bullet_jaune_2 Parameterizing the memory bank registers to support external burst flash
INTEGRATED I/Os
SERIAL INTERFACES
bullet_jaune_2 I2C basics
bullet_jaune_2 I2C controller
bullet_jaune_2 UART controller
bullet_jaune_2 SPI and SSP interfaces
bullet_jaune_2 CAN protocol basics
bullet_jaune_2 CAN controller (2294)