| Formation Processors (generic) - Multicore implementation |
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You are here: ac6 > ac6-formation > Processors (generic) > Multicore implementation |
| PG1 | Multicore implementation |
| Objectives | |||
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This course describes the multiple types of multicore implementations : SMP, AMP. |
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It details the hardware resources required to support SMP. |
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Debug issues are also studied. | ||
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ACSYS offers a large set of multicore processor trainings: ARM Cortex-A9MP (reference R6), Freescale MPC8641D (reference FC5) and MPC8572E (reference FN10). | ||
| A more detailed course description is available on request at info@ac6-formation.com | |||
| Prerequisites | |||
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Knowledge of high-end processor cores is recommended. | ||
| Outline |
| MULTIPROCESSING TYPES | |||
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AMP | ||
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SMP | ||
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BMP | ||
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Applications examples (MPC8641D, MPC8572, Virtex-4, Virtex 5) | ||
| HARDWARE REQUIREMENTS | |||
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Exclusive resource management | ||
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MMU page descriptor table, PowerPC tlbsync instruction | ||
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Multi-core interrupt controller | ||
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Inter-Processor Interrupts | ||
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Message passing | ||
| MULTITASK IN MULTI-CORE SYSTEMS | |||
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System booting | ||
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Defining shared resources and non-shared resources | ||
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Assigning a number to each core | ||
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Dispatching tasks to a particular core, static approach, dynamic approach | ||
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I/O management, consequence on driver design | ||
| CACHE COHERENCY | |||
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Software coherency (Power instructions dcbz, dcbf, dcbi, icbi) | ||
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Hardware coherency : snooping | ||
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Distinguishing two types of cache enabled area : random access vs sequential access, NUMA model | ||
| IMPLEMENTING A MULTI-CORE SYSTEM IN A XILINX VIRTEX-4 FX / VIRTEX-5 FXT FPGA | |||
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PLB basics | ||
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Exclusive resource management, lwarx/stwcx. | ||
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Implementing a multi-core interrupt controller | ||
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Synchronizing time bases | ||
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Is SMP possible in a multi-405 FPGA ? | ||
| Duration | Cost | Calendar |
| 2 days | 1250 € |
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