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| OVERVIEW |
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6-bus architecture, organization of a board based on MV64660 |
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Frequency domains, fast path between CPU and SRAM / SDRAM |
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Data integrity checking |
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Internal crossbar |
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Master de-mux programming, address decode windows |
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Slave mux programming, pizza arbiters operation |
| CPU INTERFACE |
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CPU address space decoding |
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CPU-to-PCI address remapping |
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Protection windows |
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Arbitration, multi-processor operation |
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CPU slave operation |
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Cache coherency |
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Deadlock avoidance |
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Transaction ordering |
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Hardware implementation, clocking, low power modes |
| DDR2 INTERFACE |
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Introduction to DDR SDRAM from Jedec specification |
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DDR2 on-die terminations |
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Clocking |
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Initialization sequence |
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Data synchronization : DQS signals, programmable DLL |
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DDR2 SDRAM controller, functional description |
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Page management |
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Read and write transactions |
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ECC and read-modify-write transactions |
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Hardware implementation, ODT management (internal and external) |
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Low power modes |
| DEVICE CONTROLLER |
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Transaction queue, read and write data buffers |
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Address and data multiplexing |
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Timing parameters |
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External acknowledgement |
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Pack / unpack and burst support |
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NAND flash support, boot from NAND flash |
| PCI INTERFACE |
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PCI bus arbitration |
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Master operation in PCI and PCI-X mode |
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Target operation in PCI and PCI-X mode |
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PCI-to-PCI configuration transactions |
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Address decoding |
| PCI-EXPRESS x4 AND x1 INTERFACES |
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Integrated low power SERDES PHY |
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x1, x4 link |
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Operating as either Root Complex or Endpoint |
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Link initialization |
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Arbitration and ordering |
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Peer-to-peer traffic |
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Messaging unit, synchronization between CPUs through PCI/PCI-Express |
| GENERAL PURPOSE INPUT/ OUTPUT PINS |
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GPIO port, functional description |
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Interrupt request inputs |
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Multi Purpose Pin multiplexing |
| INTERRUPT CONTROLLERS AND TIMERS |
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Watchdog timer |
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Interrupt controller functional description |
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Interrupt steering logic to 4 possible output pins |
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Priority mechanism |
| TWSI CONTROLLER AND RESET |
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Master and slave operation, 7- or 10-bit addressing |
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Determining the current state of the controller by reading the status register |
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Master write sequence, master read sequence |
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Slave write sequence, slave read sequence |
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Reset pins and configuration |
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Utilization of the boot sequencer |
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Requirement for an external Central Resource CPLD |
| IDMA CHANNELS |
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IDMA address decoding |
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Target unit and attributes programming |
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Functional description, external control |
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Normal mode vs chained mode |
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Transfer descriptors, descriptor ownership |
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Channel activation |
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DMA interrupts |
| XOR ENGINES |
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State machine : Active, Inactive and Paused states |
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XOR, CRC and DMA operation modes, format of transfer descriptors |
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XOR operation mode |
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CRC32 operation mode |
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DMA operation mode |
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Memory Initialization operation mode |
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ECC error cleanup operation mode |
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Arbitration between XOR engine0 and XOR engine1 |
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Address override capability |
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XOR Engines interrupts |
| 16550 COMPATIBLE UARTs |
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FIFO mode |
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Flow control |
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Transmit sequence |
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Receive sequence |
| USB2.0 PORTS |
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Address decoding |
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Integrated PHY |
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USB host operation, EHCI specification support |
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USB device operation, Endpoint configuration |
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Dedicated DMA for data movement between memory and port |
| SATA-II INTERFACE |
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Integrated PHY, 3.0 or 1.5 Gbps bit rate |
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EDMA request and response queues |
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Studying the sequence that the software must implement to perform a PIO transfer |
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Studying the sequence that the software must implement to perform a DMA transfer |
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Queued DMA |
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Interrupt coalescing |
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Port multiplier support |
| GIGABIT ETHERNET CONTROLLERS |
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SGMII support |
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Dedicated DMA |
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Related interrupts |
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Transmit weighted round-robin arbitration |
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Backpressure mode |
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Transmit and receive sequences |
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Management interface |
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MIB |
| CRYPTOGRAPHIC ENGINE AND SECURITY ACCELERATORS |
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Cryptographic engine functional description |
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Involved units : CPU, dedicated SRAM and security accelerator |
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Authentication |
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Encryption and decryption, supported algorithms |
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TDMA controller, attaching TDMA to security accelerator |
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Multi-packet chained mode |
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DES encryption / decryption sequence, pipelining |
