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Vous êtes ici: ac6 > ac6-formation > Network > MARVELL 88E6061/6061B/6031 Ethernet switches

NS1 MARVELL 88E6061/6061B/6031 Ethernet switches

This course covers Marvell Link Street 100 Mbps Soho switches

Objectives
bullet_jaune_1 Providing the basic knowledge on 802.3 and 802.1.
bullet_jaune_1 Understanding the parameters that determine the QoS.
bullet_jaune_1 Implementing the Dynamic Queue Limit architecture.
bullet_jaune_1 Description of the Address Lookup engine.
bullet_jaune_1 Clarifying the bridge loop prevention mechanism.
bullet_jaune_1 Becoming familiar with the API defined by Marvell.

bullet_jaune_1 This course has been delivered several times to companies involved in the design of embedded equipments.
Practical labs using the Marvell GUI allow attendees to understand the various operation modes offered by this class of switch devices.
A more detailed course description is available on request at info@ac6-formation.com
Prerequisites
bullet_jaune_2 Knowledge of IEEE 802.3 and IEEE 802.1: see our course Ethernet and switching, reference N1

Plan
100 Mbps ETHERNET BASICS
bullet_jaune_2 MAC layer
bullet_jaune_2 PHY layer
bullet_jaune_2 Auto-negotiation
802.1Q BASICS
bullet_jaune_2 Spanning tree
bullet_jaune_2 VLAN tag
bullet_jaune_2 Management functions
bullet_jaune_2 Automatic address learning
bullet_jaune_2 Handling multicasts, GVRP
INTRODUCTION TO 88E6061 SWITCHES
bullet_jaune_2 Block diagram
bullet_jaune_2 Application examples
bullet_jaune_2 Software architecture
SWITCH CORE FUNCTIONAL DESCRIPTION
bullet_jaune_2 Architecture, embedded memory
bullet_jaune_2 Operation of the integrated MACs
bullet_jaune_2 IGMP snooping
bullet_jaune_2 Ingress policy
bullet_jaune_2 Queue controller
bullet_jaune_2 Egress policy
bullet_jaune_2 Spanning tree support
bullet_jaune_2 Handling of management frames
PHY INTERFACE
bullet_jaune_2 Transmit PCS and PMA
bullet_jaune_2 Receive PCS and PMA
bullet_jaune_2 Far End Fault indication
bullet_jaune_2 Auto MDI/MDIX crossover
bullet_jaune_2 Accessing PHY registers, MDC/MDIO interface
bullet_jaune_2 Register description
bullet_jaune_2 Auto-configuration
SOFTWARE ARCHITECTURE
bullet_jaune_2 Multi-layer architecture
bullet_jaune_2 Source code organization
bullet_jaune_2 Platform specific routines
bullet_jaune_2 SMI interface functions
bullet_jaune_2 Semaphore related routines
bullet_jaune_2 Accessing global registers
bullet_jaune_2 API layer