N4	Ethernet 10 Gigabit

This course covers IEEE802.3 Ethernet 10 gigabit

OBJECTIVES The course explains the theory of Ethernet 10 Gigabit from IEEE802.3 standard. Implementation examples are provided for MAC and PHY. The hardware interfaces are fully detailed: XGMII, XAUI, XSBI and XFP. The course describes the purpose of each unit present in the transmit and receive path. Software aspects, such as 10GBASE-T autonegotiation and more generally registers implemented in PHY sublayers are also covered. Enhancement of MACs, necessary to support 10 Gigabit operation, are studied through Intel 82599 A more detailed course description is available on request at info@ac6-formation.com

PREREQUISITES
	Knowledge of Ethernel 10/100/100 is required. (see our course reference N1).

Outline

INTRODUCTION TO ETHERNET 10G Clarifying the various types of Ethernet 10G PHYs Maintaining backwards compatibility with Ethernet 10/100/1000 Mbps Full duplex only operation MAC / PHY INTERFACE XGMII transfer protocol, the 4 lanes Error and fault handling Electrical characteristics Fine granularity rate control Packet granularity rate control MAC self-pacing XGXS optional layer, increases the physical separation between the MAC and PHY 8b/10b coding scheme XAUI electrical interface INTRODUCTION TO 10G PHYS LAN PHYs WAN PHYs Backplane applications, 10GBASE-KR Clause 45 Management Input / Output interface 10GBASE-W/R PCS Introduction to SONET/SDH PCS layer, 64b/66b coding scheme (10GBASE-W/R) Mapping of 16-bit data stream to from PMA service interface Gearbox 66-bit blocks packing Defining a mechanism to adapt the MAC/PLS data rate of the WAN PHY BER monitor process WAN Interface Sublayer Framing, scrambling, defect/anomaly detection Transmitter, mapping of data-units from the PCS into the payload capacity of a STS-192c SPE Receiver, delineation of octet boundaries, checking the BIP octets Error propagation 10GBASE-W/R PHY specific registers Implementation example: AMCC QT2035 SFI/XFI-XAUI PHY and S19235 SONET/SDH transceiver with ISI compensation, highlighting the internal units 10GBASE-W/R PMA AND PMD LAYERS Bit clock recovery of serial data from PMD Link status information PMA specific registers XSBI bus Optical transmission basics 10GBASE-S, 10GBASE-L, 10GBASE-E Optical measurement requirements Characteristics of the fiber optic cabling

10GBASE-X Utilization of control characters for signalling 4 optical wavelengths, one laser for each wavelength Wave Division Multiplexing basics Transmitter, amplifier Deskew in PCS receiver Multiplexing, demultiplexing PMD block diagram 10GBASE-LX4 PMA 10GBASE-CX4 PMA 10GBASE-T 16-level PAM signaling 2D symbol selection from a constrained constellation of 128 maximally spaced 2D symbols 65B-LDPC transmission code Link training, master / slave operation Forward error correction PMA stages What is Alien NEXT, sources of Alien NEXT, Alien crosstalk noise rejection Compensating for signal attenuation Auto-negotiation, page utilization MDI specification 10G BACKPLANES 10GBASE-KX4 Electrical characteristics 10GBASE-KR Frame marker Control channel Coefficient update Electrical characteristics Autonegotiation for Ethernet backplanes, DME electrical specification MAC ENHANCEMENTS TO SUPPORT 10G Transmitter frame ordering Arbitration between queues Transmitter shaper Receiver frame filtering Selecting the ring through classification of incoming accepted frames Implementation example: Intel 82599 MAC Queuing in a Virtualized Environment Flow Director Filters Buffer allocation MAC layer offloads Direct cache access Receiver side coalescing Transmit rate scheduler

 

Duration	Cost	Calendar
3 days	0 €