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| INTRODUCTION TO MPC8XX |
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MPC8XX block diagram : the PowerPC core, the SIU and the CPM modules |
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The 3 registers families : GPRs, SPRs, and memory-mapped |
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The 860 derivatives features : 85X, 86X, 87X and 88X |
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Performance estimation |
| PowerPC CORE ARCHITECTURE |
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RCPU pipeline, history buffer, isync instruction |
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Execution units |
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Cache basics |
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Load/store architecture |
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Sync and eieio instructions |
| PowerPC CORE PROGRAMMING |
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User registers |
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Branch instructions |
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Integer load / store instructions |
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Integer arithmetic |
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The EABI |
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Code and data sections |
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Cache related instruction |
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Exception management at core level : handler table, priority |
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MMU basics |
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Tablewalk through the descriptor tables description |
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TLB entry software loading |
| THE SYSTEM INTERFACE UNIT |
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The interrupt controller |
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MPC8XX hardware configuration at reset : sampling of the configuration word |
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Clock synthesizer |
| THE EXTERNAL BUS INTERFACE |
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Dynamic bus sizing, connection of 8 and 16-bit peripherals |
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Single data read and write timing diagrams |
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Burst read and write timing diagrams |
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Shared resource control |
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Bus error, retry |
| THE MEMORY CONTROLLER |
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Address decoding through BR/OR registers |
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GPCM timing parameters explanation |
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SDRAM basics |
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Connection of an SDRAM, UPM initialization |
| CPM BASICS |
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Synchronization between RCPU and CP through the Command Register |
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DPRAM organization |
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The CPM Interrupt Controller |
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CPM general purpose timers |
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IDMA channels |
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General purpose IO : pin configuration |
| THE SERIAL INTERFACE |
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ISDN basics |
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NMSI vs TDM |
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SIRAM initialization to support ISDN frames |
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Transmit and Receive clock selection from the bank of clocks |
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Buffer Descriptor rings allocation |
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Buffer chaining |
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Transmit and receive interrupts |
