FCQ11	P102X QorIQ implementation

This course covers Freescale QorIQ P101X and P102X QorIQ SoC family

Objectives The course clarifies the architecture of the P102X, particularly the operation of the coherency module that interconnects the e500s to memory and high-speed interfaces. Cache coherency protocol is introduced in increasing depth. The e500 core is viewed in detail, especially the SPE unit that enable vector processing. The boot sequence and the clocking are explained. The course focuses on the hardware implementation of the P102X. A long introduction to DDR SDRAM operation is done before studying the DDR2/3 SDRAM controller. An in-depth description of the PCI-Express port is done. The course highlights both hardware and software implementation of gigabit / fast / Ethernet controllers. Management of E1/T1 lines by QUICC engine is explained. ACSYS has developed an optimized SPE based FFT coded in assembler language. Performance for 1024 complex floating point single precision samples is: - 91_386 core clock cycles without reverse ordering, 94_124 with reverse ordering Performance for 4096 complex floating point single precision samples is: - 470_778 core clock cycles without reverse ordering, 511_227 with reverse ordering For any information contact guillaume.peron@ac6.fr A more detailed course description is available on request at info@ac6-training.com

Prerequisites and related courses
	Experience of a 32-bit processor or DSP is mandatory.
	The following courses could be of interest:
		Ethernet and switching, reference N1
		IEEE1588, reference N2
		PCI express gen2, reference IC4
		USB Full Speed High Speed and USB On-The-Go, reference IP2
		SD / MMC, reference IS2

Outline

INTRODUCTION TO P102X OVERVIEW Internal data flows, OCEAN switch fabric, packet reordering Address map, ATMU, OCEAN configuration Local vs external address spaces, inbound and outbound address decoding Access control unit, controlling access to CCSR THE e500 CORE THE INSTRUCTION PIPELINE Execution units Dynamic branch prediction DATA AND INSTRUCTION PATHS The Core Complex Bus Store miss merging and store gathering THE MEMORY MANAGEMENT UNIT The first level MMU and the second level MMU 36-bit real addressing CACHES The L1 caches Software cache coherency Level 2 cache e500 coherency module Snooping mechanism Stashing mechanism PROGRAMMING Floating Point units, Double-Precision FP Signal Processing APU (SPU) EXCEPTIONS Book E exception handling Handler table Core timers: Decrementer, Time Base, Fixed Interval Timer and Software Watchdog DEBUGGING Performance monitoring Watchpoint logic INFRASTRUCTURE RESET, CLOCKING AND INITIALIZATION Selecting configuration options Power-on reset sequence Power-on reset configuration Power management Secure boot and trust architecture e500 COHERENCY MODULE I/O arbiter CCB arbiter DDR2/DDR3 SDRAM MEMORY CONTROLLER DDR2 and DDR3 Jedec specification On-Die termination Calibration mechanism Mode registers initialization, bank selection and precharge Bank activation, read, write and precharge timing diagrams, page mode ECC error correction Initial configuration following Power-on-Reset Timing parameters programming ENHANCED LOCAL BUS CONTROLLER Dynamic bus sizing GPCM, UPMs states machines Flash Control Machine NAND flash controller PCI EXPRESS INTERFACE Modes of operation, Root Complex / Endpoint Byte swapping Transaction ordering rules Programming inbound and outbound ATMUs PROGRAMMABLE INTERRUPT CONTROLLER PIC in multiple-processor implementation Interrupt sources Interprocessor interrupts Nesting implementation INTEGRATED DMA CONTROLLER Support for cascading descriptor chains Scatter / gathering Selectable hardware enforced coherency PERFORMANCE MONITOR AND DEBUG FEATURES Event counting Watchpoint facility Trace buffer

INPUTS/OUTPUTS THE ETHERNET CONTROLLERS Physical interfaces: GMII, MII, TBI, RGMII, SGMII Layer 2 acceleration accept or reject on address or pattern match 256-entry hash table for unicast and multicast Management of VLAN tags and priority Quality of service TCP/IP offload engine, filer programming IEEE1588 compliant time-stamping ENHANCED SECURE DEVICE HOST CONTROLLER Introduction to MMC and SD card Multi-block transfers Moving data by using the dedicated DMA controller Dividing large data transfers Card insertion and removal detection USB CONTROLLER EHCI implementation Periodic Frame List ULPI interfaces to the transceiver Dedicated DMA channels Endpoints configuration SECURITY ENGINE Introduction to DES and 3DES algorithms Data packet descriptors Crypto channels XOR acceleration LOW SPEED PERIPHERALS Description of the NS16552 compliant Uarts I2C controller Enhanced SPI controller QUICC ENGINE OVERVIEW OF QUICC ENGINE Integrated RISC CPU Communication between Host CPU and QE RISC CPU, utilization of Command Register INTEGRATED INTERRUPT CONTROLLER Priority management, understanding the priority table Managing a vector table using the hardcode ID provided by SIVR / HSIVR registers SYSTEM INTERFACE AND CONNECTION TO EXTERNAL COMMUNICATION PORTS Serial DMA NMSI vs TDM Enabling connections to TSA or NMSI Baud-rate generators QUICC engine timers BUFFER MANAGEMENT Chaining descriptors into rings Frame boundary definition Interrupt management Parameter RAM independent of protocol UNIFIED COMMUNICATION CONTROLLERS UCC feature set Handling UCC interrupts UCC as slow communications controllers, UART mode UCC for fast protocols, virtual FIFOs Defining Tx- and Rx-FIFO thresholds UCC HDLC CONTROLLER HDLC frame description Flow control Setting global parameters Describing the parameter RAM Host commands UCC TRANSPARENT CONTROLLER Transparent data encapsulation, frame sync and frame CRC Flow control Setting global parameters Describing the parameter RAM Host commands SERIAL INTERFACE Connecting TDM lines Connecting the TDM line to UCC using Rx/Tx routing tables Implementing shadow tables to dynamically switch between two different routing schemes Implementing multiframe mode to manage a large number of time slots MULTI-CHANNEL CONTROLLER ON UCC - UMCC Clarifying the various tables that must be implemented in MURAM Connecting time-slots to logical channels through Rx/Tx routing tables Implementing Rx/Tx channel buffers Interrupt management, benefits of interrupt queues Parameterizing the channels UMCC host commands

 

Duration	Cost	Calendar
6 days	2700 €