FCQ5 P4080 QorIQ implementation

This course covers Freescale QorIQ P4040 and P4080


Objectives
	This course has 6 main objectives:
		Describing the hardware implementation, particularly the boot sequence and the DDR3 controller
		Understanding the features of the internal interconnect and related units and mechanisms such as PAMU, CPC and stashing
		Describing the units which are interconnected to other modules, such as clocking, interrupt controller and DMA controller, because the boot program generally has to modify the setting of these units
		Explaining the standard bus interface controllers, PCIe, SRIO, USB and MMC-SD
		Clarifying the operation of the Datapath Acceleration Architecture that assists the processor core in taking in charge buffer allocation, queue management, frame management and particularly incoming frame classification, pattern searching, and encryption
		Describing the various debug units and their utilization to fix errors in a multicore / multimaster SoC.

	Products and services offered by ACSYS:
		ACSYS is able to assist the customer by providing consultancies
		Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
		Note that ACSYS has delivered several consultancies on Freescale Netcomm SoCs to companies developing avionic equipments.
A more detailed course description is available on request at info@ac6-training.com
This document is necessary to tailor the course to specific customer needs and to define the exact schedule.


Prerequisites
	Experience of a 32-bit processor or DSP is mandatory.
	Note that the e500mc Power core is covered in a separate course reference FCC1 .
Related courses
	Ethernet and switching, reference N1
	IEEE1588, reference N2
	10 Gigabit Ethernet, reference N3
	PCI express gen2, reference IC4
	RapidIO 2.1, reference IC5
	USB Full Speed High Speed and USB On-The-Go, reference IP2
	SD / MMC, reference IS2

Outline


P4080 ARCHITECTURE
SOC ARCHITECTURE
	Block diagram
	Internal architecture
	CoreNet coherency fabric
	Coherency subdomains
	Memory map, local access windows
	Multicore processing scenarios
SOC PLATFORM
POWER, RESET AND CLOCKING
	Power management control
	Configuration signals sampled at reset
	Reset configuration words source
	Pre-boot loader
	Clocking, system clock domains
	Dynamically changing core clocks
	SerDes high speed lanes configuration
SECURE BOOT
	Objectives of trust architecture
	Secure boot sequence
	External tamper detection
	Run time integrity checker
CORENET PLATFORM CACHES
	Operation as memory-mapped SRAM
	Partitioning between coherency domains
	Stashing
	Soft error detection and correction
PERIPHERAL ACCESS MANAGEMENT UNIT (PAMU)
	Controlling master access permissions through Logical I/O Device Number
	Address translation
	Descriptor organization
	Operation mode translation
	Steps in processing of DSA operations by pamu
	PAMU caches
MULTIPROCESSOR PERIPHERAL INTERRUPT CONTROLLER
	Interrupt nesting
	Description of the 4 timers / counters
	Message interrupts
	e500-to-e500 interrupt capability
LOW SPEED PERIPHERALS
	DUART
	I2C controller
	eSPI controller
ENHANCED SDHC
	Transfer protocol, single block, multiple block read and write
	Internal and external DMA capabilities
	SD protocol unit
	Card insertion and removal detection
USB CONTROLLERS
	USB1 host only controller, USB2 host or device controller
	EHCI support, scheduling the various transactions into frames
	ULPI interface to external PHY
	Endpoint configuration
	Non-EHCI tuning control registers
HARDWARE IMPLEMENTATION
THE DDR2/3 MEMORY CONTROLLERS
	DDR3 fly-by architecture, write leveling
	ZQ calibration
	Command truth table
	Hardware interface
	Initial configuration following Power-on-Reset
	Controller interleaving support
	Address decode unit
	Timing parameters programming
ENHANCED LOCAL BUS CONTROLLER
	Multiplexed or non-multiplexed address and data buses
	Connecting 8- and 16-bit devices
	Burst support
	GPCM, UPMs states machines
	NAND flash controller
INTEGRATED DMA CONTROLLERS
	Priority between the 4 channels
	Scatter / gathering
	Selectable hardware enforced coherency
	Ability to start DMA from external 3-pin interface
PCI EXPRESS INTERFACE
	Acting as a bridge when Root Complex
	Transaction ordering rules
	Programming inbound and outbound ATMUs
	Benefits of MSIs
	Low power management
	Configuration, initialization
	Enhanced error reporting
SERIAL RAPIDIO INTERFACE
	RapidIO port
	Message Unit, direct vs chaining mode operation
	RapidIO doorbell and port-write unit
	Programming inbound and outbound ATMUs


DATAPATH PROCESSING SUBSYSTEM
DPAA OVERVIEW
	Data formats
	Frame formats
	Packet walk through
	DPAA Configuration and initialization
QUEUE MANAGER
	Objectives if this accelerator
	Structure of frame queues
	Active and suspended frame queues
	Frame queue descriptor, frame queue descriptor cache
	Frame queue state machine
	Work queues and channels
	Enqueue and dequeue portals
	Utilization of rings
	Dequeue dispatcher operation
	Message ring
	• Congestion avoidance, Weighted Random Early Discard
	• Order definition point implementation
BUFFER MANAGER
	Objectives if this accelerator
	Central resource pool management function
	Per-pool stockpile
	CoreNET software portals
	Direct connect portals
	Buffer Pool State Change Notifications
FRAME MANAGER
	Objectives if this accelerator
	FMAN submodules
	Rx BMI features
	Tx BMI features
	Offline parsing, host command features
	Frame processing manager
	FMan controller
	Parser
	Key generator
	Policer
DATA PATH THREE-SPEED ETHERNET CONTROLLERS
	Frame format with and without VLAN option
	Connection to packet FIFO interface
	Physical interfaces
	256-entry hash table for unicast and multicast
	Accessing PHY registers
	RMON statistic counters, carry registers
	Client IEEE1588 timers
10-GIGABIT MAC
	XAUI interface to PHY
	Multicast address filtering
	Dynamic inter packet gap (IPG) calculation
	MAC address insertion
	Support for VLAN
	IEEE 1588 timestamping
SECURITY ENGINE
	Introduction to DES, 3DES and AES algorithms
	Job management using QMan interface
	Input / output rings
	Cryptographic operations
	Data movement, FIFOs
	Scatter / gather DMA
	Selecting the authentication / cryptographic algorithm
	Run Time Integrity Checking
	Example, implementing IPSec
PATTERN MATCHER
	Objective of this unit, identifying signatures in incoming gigabit streams
	Connection to QMan and BMan
	Ability to track stateful relationships between patterns found in the data it scans
	Updating the pattern database
	Definition of a regular expression
	Comparing the string under inspection with the programmed patterns
	Processing pipeline, work units
	Pattern Matcher Frame Agent
	Pattern description block caching
	Key Element Scanner
	Data Examination Engine
	Stateful Rule Engine
GLOBAL FUNCTIONS, DEVELOPMENT AND DEBUG
PERFORMANCE MONITOR AND DEBUG FEATURES
	Introduction to NEXUS specification
	NEXUS Aurora link
	Event processing unit
	Watchpoint facility
	Trace buffer
	Event Combining for the Creation of Advanced Triggers
	Cross-Functional Debug Components
	DDR SDRAM interface debug, measuring per-master bandwidth

Duration	Cost	Calendar
6 days	2700 €