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| THE TRANSITION TO PACKET SWITCHING |
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PCI bus limitations |
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PCI-X bus |
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Solutions to increase the performance : differential transmission, packet switching, gigabit serdes |
| INTRODUCTION TO RapidIO |
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System view |
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Layer model, features of logical, transport and physical layers |
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Purpose of control symbols |
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Request / response sequence |
| THE INPUT / OUTPUT LOGICAL TRAFFIC |
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Accessing memory mapped address ranges |
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Accessing the configuration space |
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Atomic transactions |
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Maintenance transaction |
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Transaction ordering |
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Transfer efficiency calculation |
| THE MESSAGE PASSING LOGICAL TRAFFIC |
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Interconnection of host domains |
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Message vs doorbell |
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Transfer efficiency calculation |
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Detail of message passing implementation in Freescale netcomm devices |
| CACHE COHERENCE |
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Cache basics |
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Snooping basics |
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Data shared by DMA and CPU through a RapidIO fabric |
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Data shared by CPUs connected to a RapidIO fabric |
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GSM transactions, coherence domains |
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The CC-NUMA approach |
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Analysis of various cache coherency sequences |
| DATA STREAMING LOGICAL SPECIFICATION |
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Data path vs control path requirements |
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Mechanism of transporting an arbitrary protocol over a standard RapidIO interface |
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Traffic streams |
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Support for PDU of 64 kB through segmentation and reassembly |
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Class of services and virtual queues |
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IP over RapidIO |
| LOGICAL LAYER FLOW CONTROL |
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Types of congestion |
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Controlled flow list |
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XON-XOFF controls on transaction request flows |
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XON-XOFF counters |
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Ordering rules |
| THE TRANSPORT LAYER |
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Common transport layer |
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Packet routing through the network based on destination ID |
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Programming interface to read / write the routing tables |
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Multicast extensions (RapidIO 1.3) |
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Hardware support for the duplication of posted write packets |
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Setting a list of egress ports in a multicast mask list |
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Associating a destination ID with the multicast mask |
| SYSTEM BRINGUP |
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System exploration and initialization |
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Winning host |
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System enumeration API |
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Enumeration time-out |
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Hardware abstraction layer |
| OVERVIEW OF THE PHYSICAL LAYER |
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Alignement rules |
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Packet acknowledgement |
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Control symbols vs packet |
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Multicast event |
| ERROR MANAGEMENT |
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Packet protection through CRC |
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Early processing of packets |
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Study of various sequences explaining the ability of RapidIO to recover from errors automatically by hardware |
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Software aspects, link maintenance request and response |
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RapidIO 1.3 added requirements in physical and logical layers |
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Error reporting thresholds |
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Port behaviour when error rate failed threshold is reached |
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Drop packet enable |
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System software notification of errors |
| PACKET PRIORITY AND FLOW CONTROL |
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Transaction ordering rules |
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Mapping flowID into 2-bit priority |
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Receiver based flow control, retry mechanism |
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Transmitter based flow control, management of transmit credits |
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Deadlock prevention |
| THE LP-LVDS 8/16 INTERFACE |
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Transfer protocol, packet and control symbol delineation |
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Insertion of symbols within packets |
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Use of eye diagram to specify the electrical interface |
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Training pattern |
| THE LP-S 1x/4x INTERFACE |
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Features or sublayers PCS and PMA |
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Single VC mode vs multiple VC mode, purpose of VC status control symbol |
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Bandwidth allocation |
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The 8b/10b encoder / decoder |
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Special characters, comma detection |
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Symbol and packet delimitation |
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Idle sequence, scrambling, descrambler synchronization |
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Lane synchronization |
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1.25Gbaud, 2.5Gbaud, and 3.125Gbaud LP-Serial Links |
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5Gbaud and 6.25Gbaud LP-Serial Links |
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Pulse response channel modelling |
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High frequency jitter vs wander |
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Transmit emphasis tuning |
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Use of eye diagram to specify the electrical interface |
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Port initializatio |
| VIRTUAL OUTPUT QUEING EXTENSIONS |
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Head Of Line blocking |
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Congestion message |
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Traffic staging |
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Relationship with VC |
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VOQ backpressure extended features register block |
