| Formation Connectivity - PCI-X 2.0 |
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Vous êtes ici: ac6 > ac6-formation > Connectivity > PCI-X 2.0 |
| IC3 | PCI-X 2.0 |
| Objectives | |||
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The course explains the architecture of PCI-X based systems. |
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The reset sequence used to select the mode (PCI or PCI-X) and the frequency is detailed. |
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The course explains split transactions. |
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Transfer protocol is described in details with the assistance of the Lecroy analyser. | ||
| A more detailed course description is available on request at info@ac6-training.com | |||
| Prerequisites | |||
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Knowledge of PCI 3.0: see our course reference IC1 |
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| Plan |
| INTRODUCTION TO PCI-X | |||
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PCI restrictions : data rate is not sufficient for Fibre Channel, Ultra SCSI or Gigabit Ethernet applications | ||
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PCI-X technology overview | ||
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Segments and switched fabric | ||
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Relationship between the number of slots and the operation frequency | ||
| ELECTRICAL SPECIFICATION | |||
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Register / register approach, effect on the performance | ||
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Current / voltage curves | ||
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Decoupling rules | ||
| PCI-X DEVICE HARDWARE CONFIGURATION AT RESET | |||
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PCIXCOMP pin utility | ||
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Behavior of a PCI-X motherboard when a PCI board is present | ||
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Behavior of a PCI-X expansion board when it is plugged in a PCI motherboard | ||
| TRANSFER PROTOCOL | |||
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New commands | ||
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Alignment rules | ||
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PCI MEM space address decoding | ||
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Attribute phase | ||
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Split transactions | ||
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Sequence numbering | ||
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Data cachability indication | ||
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Exclusive access | ||
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Arbitration, bus parking | ||
| CONFIGURATION REGISTERS | |||
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Capability list PCI-X structure | ||
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New registers description | ||
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Bus error management | ||
| Durée | Prix | Calendrier |
| 2 jours | 1250 € |
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