| Formation Connectivity - Serial ATA III |
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You are here: ac6 > ac6-formation > Connectivity > Serial ATA III |
| IS3 | Serial ATA III |
| Objectives | |||
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This course explains how SATA maintains compatibility with IDE software management . |
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The hardware layer is detailed, including the analog part and Out-Of-Band signals operation. |
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The FIS is analyzed in order to understand the dialog between Host Controller and mass storage device. |
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The course clarifies the programming interface specified by the Advanced Host Controller Interface . |
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The Gen3 physical layer specification and testing requirements are particularly detailed. |
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The course describes the low power modes. | ||
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It has been delivered several times to companies developing SoCs for wireless / consumer market. |
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| Timing diagrams are taken from a PC implementing a SATA interface thanks to the Lecroy analyser. |
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| A more detailed course description is available on request at info@ac6-training.com | |||
| Prerequisites | |||
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Experience of a serial bus like USB or Ethernet is recommended. |
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| Outline |
| ORIGINS OF THE SATA INTERFACE | |||
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Parallel ATA limitations | ||
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Faster HDD access and logical block addressing (LBA) | ||
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ATAPI for support of other peripheral devices | ||
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Programmed Input / output, direct memory access (UDMA) | ||
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Revisions of the SATA specification | ||
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Compatibility with SAS | ||
| SATA ARCHITECTURE | |||
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Architectural layering | ||
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Hot plugging | ||
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Port multiplier | ||
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Usage model description | ||
| PHYSICAL LAYER | |||
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Cable and connectors | ||
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Analog front end | ||
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Electrical signalling | ||
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Separate point-to-point AC-coupled LVDS links | ||
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Spread Spectrum Clocking | ||
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Elastic buffer | ||
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Loopback mode | ||
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Test pattern requirements | ||
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Testing Gen3 | ||
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Jitter considerations | ||
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Explaining the various tests used to qualify transmitter and receiver | ||
| OUT-OF BAND AND PHY POWER STATES | |||
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COMRESET sequence | ||
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COMINIT sequence | ||
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COMWAKE sequence | ||
| LINK LAYER | |||
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8b/10b coding | ||
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Scrambling | ||
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Primitives description and utilization | ||
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Arbitration sequence | ||
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FIS flow control | ||
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Transitions to low power modes | ||
| ATA REGISTERS | |||
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PATA emulation | ||
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Interrupt virtualization | ||
| TRANSPORT LAYER | |||
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Introduction to FIS transfer | ||
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Interaction with Command layer | ||
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Retry protocol | ||
| PHY INTERFACE FOR SATA 3 (PIPE) | |||
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Possible PIPE clocks and data bus widths | ||
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Reset sequence | ||
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Power management | ||
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Changing signalling rate | ||
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Error detection | ||
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Loopback | ||
| ADVANCED HOST CONTROLLER INTERFACE (AHCI 1.3) | |||
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System memory structures | ||
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Native Command Queuing | ||
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FIS-based switching | ||
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Command completion coalescing | ||
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Power management | ||
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Interrupt management | ||
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Data transfer operation | ||
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Error reporting | ||
| COMMANDS | |||
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ATA-8 command set | ||
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Reset protocol, diagnostic protocol, PIO protocol, DMA protocol, PACKET protocol | ||
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First party DMA | ||
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Boot sequence capture and analyzis | ||
| Duration | Cost | Calendar |
| 2 days | 1400 € |
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