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IS3 Serial ATA III

This course covers SATA III


formateur
Objectives
bullet_jaune_1 This course explains how SATA maintains compatibility with IDE software management.
bullet_jaune_1 The hardware layer is detailed, including the analog part and Out-Of-Band signals operation.
bullet_jaune_1 The FIS is analyzed in order to understand the dialog between Host Controller and mass storage device.
bullet_jaune_1 The course clarifies the programming interface specified by the Advanced Host Controller Interface programming interface.
bullet_jaune_1 The course describes the low power modes.
Timing diagrams are taken from a PC implementing a SATA interface thanks to the Lecroy analyser.
A more detailed course description is available on request at info@ac6-training.com
Prerequisites
bullet_jaune_2 Experience of a serial bus like USB or Ethernet is recommended.

Plan
ORIGINS OF THE SATA INTERFACE
bullet_jaune_2 Parallel ATA limitations
bullet_jaune_2 Serial ATA roadmap
bullet_jaune_2 Enhanced Integrated Drive Electronics (EIDE)
bullet_jaune_2 Faster HDD access and logical block addressing (LBA)
bullet_jaune_2 ATAPI for support of other peripheral devices
bullet_jaune_2 Programmed Input / output, direct memory access (UDMA)
bullet_jaune_2 Revisions of the SATA specification
bullet_jaune_2 Compatibility with SAS
SATA ARCHITECTURE
bullet_jaune_2 General overview, topology, connectivity
bullet_jaune_2 Architectural layering
bullet_jaune_2 Standard ATA emulation
bullet_jaune_2 Flow control
TRANSPORT LAYER
bullet_jaune_2 Frame and Frame Information Structure (FIS)
bullet_jaune_2 Introduction to FIS transfer
bullet_jaune_2 Interaction with Command layer
bullet_jaune_2 Device transport states
LINK LAYER
bullet_jaune_2 Transmission words
bullet_jaune_2 8b/10b coding basics, clock recovery, code-group alignment
bullet_jaune_2 Framing concepts
bullet_jaune_2 Scrambling
PHYSICAL LAYER
bullet_jaune_2 Cable and connectors
bullet_jaune_2 eSATA
bullet_jaune_2 Separate point-to-point AC-coupled LVDS links
bullet_jaune_2 Spread Spectrum Clocking
bullet_jaune_2 Link initialization, speed negotiation
bullet_jaune_2 Power and signal lines
bullet_jaune_2 Out-of-band signalling
POWER MANAGEMENT
bullet_jaune_2 Interface power states
bullet_jaune_2 Power management primitives
bullet_jaune_2 Comwake signal sequence
HIGH LEVEL OPERATION
bullet_jaune_2 Device command layer protocol
bullet_jaune_2 Host adapter register interface
bullet_jaune_2 Error handling
ADVANCED HOST CONTROLLER INTERFACE
bullet_jaune_2 Operating modes
bullet_jaune_2 Native Command Queuing
bullet_jaune_2 Interrupt management
bullet_jaune_2 Data transfer operation
bullet_jaune_2 Hot plug management
bullet_jaune_2 Error reporting
TESTING AND VERIFICATION
bullet_jaune_2 Serial ATA analysers
bullet_jaune_2 Traffic capture
bullet_jaune_2 Test and verification of SATA devices