| Formation ARM cores - ARM fundamentals |
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You are here: ac6 > ac6-formation > ARM cores > ARM fundamentals |
| R0 | ARM fundamentals |
| Objectives | |||
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ARM modes state machine is detailed, clarifying the register banking mechanism. |
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Subtelties of ARM instruction set are covered, such as conditional execution, addressing modes, operand shifting. |
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Interworking between ARM and Thumb instruction sets is explained. |
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The exception mechanism is studied, particularly interrupt nesting. |
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The course also covers ARM926EJ-S cache and MMU operation. |
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| Labs are run under RVDS |
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| A more detailed course description is available on request at info@ac6-training.com | |||
| Prerequisites | |||
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Basic knowledge of CPU or DSP. |
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This one-day course has been designed to meet the pre-requisites of ARM11 and Cortex-A/R courses. This is a summary of ARM7/9 course. |
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| Outline |
| THE ARM V4T / V5TE ARCHITECTURE | |||
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ARM operation modes | ||
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The ARM registers set, register organization summary according to the current mode | ||
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Program Status Registers | ||
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Exception handling, vector table, automatic switch into ARM mode | ||
| ARM AND THUMB INSTRUCTION SETS | |||
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Conditional execution and flags | ||
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Branch instructions | ||
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The barrel shifter | ||
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Immediate constants | ||
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Single register data transfer | ||
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Stack management | ||
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Register access in Thumb | ||
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ARM architecture V5TE new instructions | ||
| ARM / THUMB INTERWORKING | |||
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Switching between states | ||
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Mixing ARM and Thumb subroutines | ||
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ARM to thumb veneer | ||
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Thumb-to-ARM veneer | ||
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Interworking calls | ||
| EXCEPTION HANDLING | |||
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Exception priority | ||
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Vector table instructions | ||
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Chaining exception handlers | ||
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FIQ vs IRQ | ||
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Example C interrupt handler | ||
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Issues when reenabling interrupts | ||
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C nested interrupt example | ||
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Data abort with memory management | ||
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Adjusting the return address | ||
| MEMORY MANAGEMENT & PROTECTION | |||
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Introduction to page management | ||
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Translation Lookaside Buffer | ||
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Benefits of Fast Context Switch Extension | ||
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ARM926 MMU | ||
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Organization of page descriptor tables | ||
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Configuration & control through CP15 | ||
| MEMORY SUBSYSTEMS | |||
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Cache basics | ||
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Hit under miss and its consequence: out of order abort | ||
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Highlighting data flows between main memory and caches | ||
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Write buffer | ||
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Tightly coupled memories | ||
| Duration | Cost | Calendar |
| 1 days | 700 € |
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