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This course has been designed for programmers wanting to develop algorithm based on hardware floating point calculations.
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Each instruction family is detailed, first at assembly level, and then at C level using macros. |
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Several tricky usage of vector instructions are provided.
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The underlying cache operation as well as preload mechanisms (instruction and hardware prefetch) are detailed to explain how a processing can be pipelined .
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The course shows how DSP typical algorithms such as FIR and FFT can be vectorized and then optimized to be executed on VFP unit. |
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THIS COURSE IS PROPOSED EITHER AS AN INSTRUCTOR-LED COURSE OR AS E-LEARNING. |
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ACSYS has developed an optimized VFP based FFT coded in assembler language |
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performance for 1024 complex floating point single precision samples is 220_000 core clock cycles (ARM11) |
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for any information contact guillaume.peron@ac6.fr |