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| INTRODUCTION TO P20X0 |
| Overall description |
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Internal data flows, OCEAN switch fabric, packet reordering |
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Implementation examples |
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Address map, ATMU, OCEAN configuration |
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Local vs external address spaces, inbound and outbound address decoding |
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Accessing memory-mapped registers from external master |
| THE e500 CORES |
| THE INSTRUCTION PIPELINE |
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Dual-issue superscalar control, out-of-order execution |
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Execution units : 2 simple Integer Units + 1 Complex Integer Unit |
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Dynamic branch prediction using a 128-set 4-way set associative Branch Target Buffer |
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Execution timing, rename register operation, instruction serialization |
| DATA AND INSTRUCTION PATHS |
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The Core Complex Bus : high speed on-chip local bus with data tagging |
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The LMQ, the store queue, the castout queue |
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Store miss merging and store gathering |
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Memory access ordering |
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Lock acquisition and import barriers |
| THE MEMORY MANAGEMENT UNITS |
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The first level MMU and the second level MMU, consistency between L1 and L2 TLBs |
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Snooping of TLBs |
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TLB software reload, page attributes WIMGE |
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Process protection, variable number of PID registers and sharing |
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MMU implementation in real-time sensitive applications |
| CACHES |
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The L1 caches, PLRU replacement algorithm, 8-way set associativity, cache block and unlock APU |
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Level 2 cache, partition into L2 cache plus SRAM |
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Allocation of data transferred by external masters into the cache: stashing |
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Snooping mechanism, stashing mechanism |
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L2 cache locking |
| PROGRAMMING |
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Differences between the new Book E architecture and the classic PowerPC architecture |
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Floating Point units, Double-Precision FP |
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Signal Processing APU (SPU) : implementation of the SIMD capability without using a separate unit |
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PowerPC EABI : sections, C-to-assembly interface |
| EXCEPTIONS |
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Book E exception handling |
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Critical versus non critical |
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Handler table |
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Exception nesting, recoverability from interrupt |
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Core timers : Decrementer, Time Base, Fixed Interval Timer and Software Watchdog |
| DEBUGGING |
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Performance monitoring, counting of events |
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JTAG emulation, real time trace when the e500 core executes cached instructions |
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Watchpoint logic, triggering capabilities based on user programmable events |
| INFRASTRUCTURE |
| RESET, CLOCKING AND INITIALIZATION |
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Platform clock |
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Voltage configuration selection |
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Power-on reset sequence, using the I2C interface to access serial ROM |
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Boot page translation |
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eSDHC boot |
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eSPI boot ROM |
| e500 COHERENCY MODULE |
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I/O arbiter |
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CCB arbiter |
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Transaction queue |
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CCB interface |
| DDR2/DDR3 SDRAM MEMORY CONTROLLER |
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DDR2 and DDR3 Jedec specification |
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On-Die termination |
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Mode registers initialization, bank selection and precharge |
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Command truth table |
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Bank activation, read, write and precharge timing diagrams, page mode |
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Introduction to the DDR-SDRAM controller |
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Initial configuration following Power-on-Reset |
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Timing parameters programming |
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Initialization routine |
