| Formation Connectivity - VME |
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Vous êtes ici: ac6 > ac6-formation > Connectivity > VME |
| IC7 | VME |
| Objectives | |||
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This course is based on the ANSI-VITA 1 1994 specification and ANSI-VITA 1.1 extensions. |
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The new 2eSST protocol is also described. |
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The training highlights synchronization methods like mailbox generally used in VME based calculators. |
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The daisy-chain acknowledge mechanism is viewed in detail. |
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Shared resource management is also emphasized. |
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The training shows how to configure a VME backplane. |
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After having reminded the 68K interrupt management, the VME priority interrupt bus is described. |
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VME timing diagrams are studied with the assistance of the VSYSTEMS analyser board. |
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The course focuses on the configuration space specified in the VME64 and VME64x standards. | ||
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This course has been delivered several times to companies developing defence and avionics equipments. | ||
| A more detailed course description is available on request at info@ac6-training.com | |||
| Prerequisites | |||
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Experience of a parallel digital bus is recommended. | ||
| Plan |
| INTRODUCTION TO THE VME BUS | |||
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VME based calculator architecture | ||
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Connectors pinout | ||
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The four bus parts | ||
| THE ARBITRATION BUS | |||
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Explanation of the daisy-chain acknowledge mechanim | ||
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RRS, PRI and ONE Arbiter options | ||
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RWD, ROR, FAIR requester options | ||
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Arbitration sequence analysis | ||
| THE DATA TRANSFER BUS | |||
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Byte locations accessed during a data transfer | ||
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Address pipelining | ||
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Burst transfers | ||
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Address Only transactions | ||
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BTO timer utility | ||
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Shared resource management | ||
| THE INTERRUPT BUS | |||
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Interrupt generator structure | ||
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Interrupt handler structure | ||
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Status/ID read cycle | ||
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ROAK and RORA interrupt generator options | ||
| THE UTILITY BUS | |||
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SYSFAIL management | ||
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Reset timing diagram | ||
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Power control | ||
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Auto system controller | ||
| ELECTRICAL SPECIFICATION | |||
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The 5 signal types | ||
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Bus driving and receiving requirements | ||
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Noise margins | ||
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Board powering, current ratings for power pins | ||
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Line terminations | ||
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The ETL transceiver logic required for 2eSST | ||
| THE CONFIGURATION SPACE | |||
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Determination of the mapping of the A24 config space | ||
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Detail of the CR and CSRs | ||
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Auto slot ID mechanism | ||
| VME64x EXTENSIONS | |||
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New P0/J0 connector | ||
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P1/J1, P2/J2 connectors pinouts, rows z and d pin assignments | ||
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Live insertion support | ||
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EMC front panel and subracks | ||
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ESD protection | ||
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ETL technology | ||
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2eVME protocol | ||
| 2eSST PROTOCOL | |||
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3U and 6U implementations | ||
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Broadcast transfers | ||
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Source synchronous transfers, data centered strobes | ||
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Skew calculation | ||
| Durée | Prix | Calendrier |
| 4 jours | 1950 € |
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