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Formation Marvell bridges - MARVELL MV6446X implementation
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MV1 MARVELL MV6446X implementation

This course covers Marvell Discovery III devices

Objectives
bullet_jaune_1 The course describes the MV6446X internal data paths.
bullet_jaune_1 The course explains how the host PowerPC and a CPU connected to PCI-X can synchronize to each other through the message unit.
bullet_jaune_1 A long introduction to DDR SDRAM is done prior to describe the DDR SDRAM controller operation.
bullet_jaune_1 The course focuses on the hardware implementation of the DDR SDRAM.
bullet_jaune_1 The training explains how to implement chained DMA transfers, by using either IDMA channels or XOR engines.
bullet_jaune_1 The course highlights the possible optimizations that can be implemented to boost the performance of the Ethernet controller.
bullet_jaune_1 This course has been delivered several times to companies developing defence and avionics systems.
A more detailed course description is available on request at info@ac6-formation.com
Prerequisites
bullet_jaune_2 Knowledge of PowerPC 60X / MPX bus. See our courses on Freescale and IBM Microelectronics PowerPCs.
Related courses
bullet_jaune_2 Ethernet and switching, reference N1
bullet_jaune_2 PCI, reference IC1
bullet_jaune_2 PCI-X, reference IC3
Outline
OVERVIEW
bullet_jaune_2 5-bus architecture, organization of a board based on MV6446X
bullet_jaune_2 Frequency domains, fast path between CPU and SRAM / SDRAM
bullet_jaune_2 Data integrity checking
bullet_jaune_2 Internal crossbar
bullet_jaune_2 Headers retarget
CPU INTERFACE
bullet_jaune_2 CPU address space decoding
bullet_jaune_2 CPU-to-PCI address remapping
bullet_jaune_2 Arbitration, multi-processor operation
bullet_jaune_2 Cache coherency
bullet_jaune_2 Transaction ordering
bullet_jaune_2 Hardware implementation
INTEGRATED SRAM
bullet_jaune_2 Functional description, SRAM access arbitration
bullet_jaune_2 Write-Through vs CopyBack coherency
bullet_jaune_2 ECC protection
DDR INTERFACE
bullet_jaune_2 Introduction to DDR SDRAM from Jedec specification
bullet_jaune_2 Initialization sequence
bullet_jaune_2 Page management
bullet_jaune_2 Read and write transactions
bullet_jaune_2 Transaction ordering
bullet_jaune_2 Cache coherency
bullet_jaune_2 ECC and read-modify-write transactions
bullet_jaune_2 Hardware implementation, SSTL technology
DEVICE CONTROLLER
bullet_jaune_2 Functional description, transaction queue, read and write data buffers
bullet_jaune_2 Connecting 8/16/32 bit devices
bullet_jaune_2 Timing parameters
bullet_jaune_2 External acknowledgement
bullet_jaune_2 Pack / unpack and burst support
PCI INTERFACE
bullet_jaune_2 PCI bus arbitration
bullet_jaune_2 Master operation in PCI and PCI-X mode
bullet_jaune_2 Target operation in PCI and PCI-X mode
bullet_jaune_2 PCI-to-PCI configuration transactions
bullet_jaune_2 Address decoding
bullet_jaune_2 Cache coherency
bullet_jaune_2 Messaging unit
GENERAL PURPOSE INPUT/ OUTPUT PINS
bullet_jaune_2 Pin direction and polarity definition
bullet_jaune_2 Interrupt request inputs
bullet_jaune_2 Multi Purpose Pin multiplexing
INTERRUPT CONTROLLERS AND TIMERS
bullet_jaune_2 Watchdog timer
bullet_jaune_2 Timers / counters
bullet_jaune_2 Interrupt controller functional description
TWSI CONTROLLER AND RESET
bullet_jaune_2 Master and slave operation, 7- or 10-bit addressing
bullet_jaune_2 Master write sequence, master read sequence
bullet_jaune_2 Slave write sequence, slave read sequence
bullet_jaune_2 Reset pins and configuration
bullet_jaune_2 Serial ROM initialisation
bullet_jaune_2 Requirement for an external Central Resource CPLD
IDMA CHANNELS
bullet_jaune_2 IDMA address decoding
bullet_jaune_2 Demand mode
bullet_jaune_2 Normal mode vs chained mode
bullet_jaune_2 Channel activation
XOR ENGINES
bullet_jaune_2 State machine : Active, Inactive and Paused states
bullet_jaune_2 XOR, CRC and DMA operation modes, format of transfer descriptors
bullet_jaune_2 Memory Initialization operation mode
bullet_jaune_2 ECC error cleanup operation mode
bullet_jaune_2 Address decode windows
bullet_jaune_2 Address override capability
bullet_jaune_2 Cache coherency
MULTI-PROTOCOL SERIAL CONTROLLERS
bullet_jaune_2 Address decoding
bullet_jaune_2 Pinout, connection to MPP logic
bullet_jaune_2 Baud Rate Generator
bullet_jaune_2 MPSC clocking
bullet_jaune_2 SDMA operation
bullet_jaune_2 Transmit descriptor format, ring organization
bullet_jaune_2 Receive descriptor format, ring organization
bullet_jaune_2 HDLC mode, UART mode, Transparent mode
GIGABIT ETHERNET CONTROLLERS
bullet_jaune_2 Interface to the PHY
bullet_jaune_2 Dedicated DMA
bullet_jaune_2 Transmit weighted round-robin arbitration
bullet_jaune_2 Backpressure mode
bullet_jaune_2 Transmit and receive sequences
bullet_jaune_2 Management interface
bullet_jaune_2 MIB
bullet_jaune_2 Synchronous FIFO interface
bullet_jaune_2 DMA operation
 
Duration Cost Calendar
4 days 1950 € Session calendar
 

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Last site update: Mon 21 May 2012 05:28:46 PM CEST