V1 | Les bases du langage VHDL |
Exercise : | Understanding the steps of design and programming | |
Exercise : | Getting started with the simulator, waveform generation and analysis |
Exercise : | Importing a predefined hardware definition in the project, instantiating a component |
Exercise : | Coding, simulating and synthesizing a bounds enforcer | |
Exercise : | Designing a 7-segment decoder | |
Exercise : | Designing a 4-bit adder |
Exercise : | Coding, simulating and synthesizing a bounds enforcer | |
Exercise : | Designing a 7-segment decoder | |
Exercise : | Designing a 4-bit adder |
Exercise : | Designing a counter/decounter | |
Exercise : | Designing a FIFO |
Exercise : | Designing a generic 4-digits BCD-counter and displaying it on a 7-segment display | |
Exercise : | Enhancing a 4-bit BCD-counter/decounter to create a generic one | |
Exercise : | Working with configurations | |
Exercise : | Designing a n digits BCD-counter/decounter and displaying it on a 7-segment display |
Exercise : | Designing and testing a logical address decoder | |
Exercise : | Simulation of sequential processes | |
Exercise : | Advanced simulation techniques Text files |