| Formation Freescale ARM CPUs - i.MX31 implementation + LTIB |
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You are here: ac6 > ac6-formation > Freescale ARM CPUs > i.MX31 implementation + LTIB |
| FA2 | i.MX31 implementation + LTIB |
| Objectives | |||
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The course details the hardware implementation of the i.MX31 microcontroller. |
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The boot sequence and the clocking are explained. |
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The course explains all parameters that affect the performance of the system in order to easily perform the final tuning. |
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A description of all internal peripherals is provided. |
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An overview of the ARM1136 core helps to understand issues caused by cache and MMU. |
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The course ends with practical labs explaining how to generate a Linux image as well as a Root File System, by using a tool called LTIB [Linux Target Image Builder]. | ||
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Products and services offered by ACSYS: |
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ACSYS has developed FFTs (floating-point and fixed-point) optimized for ARM cores, based on SIMD instructions supported by the ARM1136. |
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Contact guillaume.peron@ac6.fr to obtain informations about the performance of these FFTs. | ||
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ACSYS is able to assist the customer by providing consultancies. Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning. |
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ACSYS has also an expertise in programming the SDMA, a simple OS-agnostic driver has been developed to explain how to manage scripts. | ||
| This course has been delivered several times to companies developing multimedia equipments. | |||
| Program examples have been developed by ACSYS to explain the boot sequence and the operation of complex peripherals. •They are compiled by the GNU compiler and are executed under Lauterbach debugger. •A host desktop running Linux is used to generate Linux image and Root File System during labs on LTIB. |
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| A more detailed course description is available on request at info@ac6-training.com | |||
Related courses |
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| Prerequisites | |||
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Knowledge of ARM1136JF-S is recommended, see our course reference R2. |
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Knowledge of USB is recommended, see our course reference IP2 |
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ACSYS also offer a large set of courses on Linux. | ||
| Outline |
| ARCHITECTURE OF i.MX31 | |||
| Overview | |||
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Clarifying the internal data paths : AHB bus, peripheral buses | ||
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Highlighting the purpose of the 2 central interconnect units : MAX and M3IF | ||
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Organization of a board based on i.MX31 | ||
| ARM11 PLATFORM | |||
| THE ARM1136JF-S CORE | |||
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Presentation of the core, architecture and programming model | ||
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Operating modes : user, system, super, IRQ, FIQ, undef and abort | ||
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ARM vs Thumb instruction sets, interworking | ||
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Branch instructions, implementation of C call and return statements | ||
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Level1 cache operation | ||
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Memory management unit | ||
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C-to-Assembly interface | ||
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Exception mechanism, handler table | ||
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Debug facilities | ||
| THE ARM11 PLATFORM | |||
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MAX parameterizing | ||
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ARM Vector Interrupt Controller | ||
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Level 2 cache operation | ||
| HARDWARE IMPLEMENTATION | |||
| RESET AND CLOCKING | |||
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Clock distribution | ||
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PLL output frequency calculation | ||
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Power-up sequence | ||
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Low power modes, clock gating | ||
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Global reset vs warm reset | ||
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System boot mode selection | ||
| SYSTEM CONTROL | |||
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GPIO module | ||
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General Purpose Input interrupt request capability | ||
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Signal description | ||
| ACCESSING EXTERNAL MEMORIES | |||
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Description of the Master Arbitration and Buffering [MAB] unit | ||
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Description of the M3IF arbitration [M3A] | ||
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Introduction to DDR SDRAM | ||
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Enhanced DDR SDRAM controller | ||
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NAND flash controller, boot from flash | ||
| STANDARD PARALLEL INTERFACES | |||
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ATA controller | ||
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MSHC | ||
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SDHC | ||
| MULTIMEDIA UNITS | |||
| SMART DMA CONTROLLER | |||
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Scheduler | ||
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CRC calculation unit | ||
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SDMA initialisation | ||
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Instruction description | ||
| VIDEO PROCESSING UNITS | |||
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Video acquisition | ||
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MPEG4 encoder | ||
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Image Processing Unit | ||
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Graphics accelerator | ||
| AUDIO RELATED INTERFACES | |||
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SSI interfaces | ||
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Digital audio multiplexor | ||
| COMMUNICATION CONTROLLERS | |||
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1-wire interface | ||
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Configurable SPI | ||
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I2C interfaces | ||
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UART | ||
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USB | ||
| LTIB | |||
| GENERATING THE LINUX KERNEL IMAGE | |||
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Introducing the tools required to generate the kernel image | ||
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What is required on the host before installing LTIB | ||
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Common package selection screen | ||
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Common target system configuration screen | ||
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Building a complete BSP with the default configurations | ||
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Creating a Root Filesystems image | ||
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Re-configuring the kernel under LTIB | ||
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Selecting user-space packages | ||
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Setup the bootloader arguments to use the exported RFS | ||
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Debugging Uboot and the kernel by using Trace32 | ||
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Command line options | ||
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Adding a new package | ||
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Other deployment methods | ||
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Creating a new package and integrating it into LTIB | ||
| Duration | Cost | Calendar |
| 4 days | 1500 € |
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