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Clarifying the internal data paths : AHB bus, peripheral buses |
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Highlighting the purpose of the 2 central interconnect units : MAX and M3IF |
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Organization of a board based on i.MX31 |
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Presentation of the core, architecture and programming model |
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Operating modes : user, system, super, IRQ, FIQ, undef and abort |
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ARM vs Thumb instruction sets, interworking |
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Branch instructions, implementation of C call and return statements |
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Exception mechanism, handler table |
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ARM Vector Interrupt Controller |
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PLL output frequency calculation |
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Low power modes, clock gating |
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Global reset vs warm reset |
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System boot mode selection |
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General Purpose Input interrupt request capability |
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Description of the Master Arbitration and Buffering [MAB] unit |
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Description of the M3IF arbitration [M3A] |
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Introduction to DDR SDRAM |
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Enhanced DDR SDRAM controller |
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NAND flash controller, boot from flash |