STR5 STM32 F1-Series implementation

This course covers STM32F100XX, STM32F101XX, STM32F103XX, STM32F105XX and STM32F107XX ARM-based MCU family


Objectives
	This course has 5 main objectives:
		Describing the hardware implementation and highlighting the pitfalls
		Describing the ARM Cortex-M3 core architecture
		Becoming familiar with the IDE and low level programming
		Describing the units which are interconnected to other modules, such as clocking, interrupt controller and DMA controller, because the boot program generally has to modify the setting of these units
		Describing independent I/O modules and their drivers.

	Note that this course has been designed from the architecture of the most complex STM32 F1-Series device, the STM32F107.
	Consequently, a chapter has been designed by Acsys for each possible integrated IP.
		According to the actual reference chosen by the customer, some chapters may be removed.

	Products and services offered by ACSYS:
		ACSYS is able to assist the customer by providing consultancies. Typical expertises are done during board bringup, hardware schematics review, software debugging, performance tuning.
		ACSYS has also an expertise in FreeRTOS porting and uIP /LWIP stack or Interniche stack integration.
A lot of programming examples have been developed by ACSYS to help the attendee to become familiar with the IDE he has chosen.
That is why the labs included in this course can be compiled and executed under 3 possible IDEs: IAR, Keil and GCC / Lauterbach Trace32.
A more detailed course description is available on request at info@ac6-training.com
This document is necessary to tailor the course to specific customer needs and to define the exact schedule.


Prerequisites and related courses
	This course provides an overview of the ARM Cortex-M3 core. Our course reference RM2 details the operation of this core.
	The following courses could be of interest:
		USB Full Speed High Speed and USB On-The-Go, reference IP2
		Ethernet and switching, reference N1
		IEEE1588, reference N2
		CAN bus, reference IA1
		SD / MMC, reference IS2

Plan


ARCHITECTURE OF STM32F2 MCUs
	ARM core based architecture
	Description of STM32F10X SoC architecture
	Clarifying the internal data and instruction paths: AHB-lite interconnect, peripheral buses, AHB-to-APB bridges
	Integrated memories
	SoC mapping
THE ARM CORTEX-M3 CORE
	V7-M core family
	Core architecture
	Programming
	Exception behavior, exception return
	Basic interrupt operation, micro-coded interrupt mechanism
BECOMING FAMILIAR WITH THE IDE
	Acsys covers 3 IDEs: Keil, IAR and GCC / Lauterbach
	Thus the customer has just to indicate which one he has chosen
		Getting started with the IDE
		Parameterizing the compiler / linker
		Creating a project from scratch
		C start program
PROGRAMMING AND DEBUGGING
	Debug interface
	Programming
RESET, POWER AND CLOCKING
	Power control
	Reset
	Clocking
	Low power modes
INTERNAL INTERCONNECT
	Bus matrix
	DMA
HARDWARE IMPLEMENTATION
	Power pins
	Pinout
	GPIO module
	External Interrupts
INTEGRATED MEMORIES
	Embedded flash memory
	Internal SRAM
MEMORY INTERFACE
	SDIO
	Flexible Static Memory Controller
TIMERS
	Advanced-control timers TIM1 and TIM8
	General-purpose timers (TIM2 to TIM5)
	General-purpose timers (TIM9 to TIM14)
	Basic timers (TIM6 and TIM7)
	Real Time Clock
	Independent Watchdog
	Window Watchdog
ANALOG MODULES
	12-bit Analog-to-Digital Converter and Programmable Gain Amplifier
	12-bit Digital-to-Analog Converter
SECURITY AND INTEGRITY
	CRC calculation unit
	Device Electronic Signature
CONNECTIVITY AND COMMUNICATION
	SPI
	SPI in I2S mode
	UART
	I2C
	bxCAN modules
	USB FS
	Fast ethernet with IEEE1588
	ISO7816 smartcard interface

Durée	Prix	Calendrier
5 jours	1950 €